Mustafa Celik

PRIMA: passive reduced-order interconnect macromodeling algorithm

This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the block Arnoldi technique to include guaranteed passivity. Moreover, it is empirically observed that the accuracy is superior to existing block Arnoldi methods. While the same passivity extension is not possible for MPVL, we observed comparable accuracy in the frequency domain for all examples considered. Additionally a path tracing algorithm is used to calculate the reduced order macromodel with the utmost efficiency for generalized RLC interconnects.

Electromagnetic model order reduction for system-level modeling

Reduced-order modeling of an electromagnetic system is understood as the approximation of a continuous or discrete model of the system by one of substantially lower order, yet capable of capturing the electromagnetic behavior of the original one with sufficient engineering accuracy. Specific methodologies for model order reduction of distributed electromagnetic systems are discussed in this paper. It is shown that electromagnetic model order reduction enhances computational efficiency and, thus, facilitates system-level modeling and computer simulation of multifunctional systems. The proposed methodologies are demonstrated through applications to the reduced-order modeling of high-speed interconnects, electromagnetic waveguides, and microstrip antennas.

SPIE: sparse partial inductance extraction

Extracting the inductance of complex interconnect topologiesis a formidable task, and simulating the resulting dense partialinductance matrix is even more difficult. Furthermore, it is wellknown that simply discarding smallest terms to sparsify the inductancematrix can render the partial inductance matrix indefiniteand result in an unstable circuit model. In this paper, wedescribe a methodology for incrementally generating a sparsepartial inductance matrix based on using moments about s=0 todetermine when a sufficient number of mutual inductances havebeen captured. The minimally required mutual inductances areextracted for a provably stable model.

Practical considerations for passive reduction of RLC circuits

Krylov space methods initiated a new era for RLC circuit model order reduction. Although theoretically well-founded, these algorithms can fail to produce useful results for some types of circuits. In particular controlling accuracy and ensuring passivity are required to fully utilize these algorithms in practice. In this paper we propose a methodology for passive reduction of RLC circuits based on extensions of PRIMA, that is both broad and practical. This work is made possible by uncovering the algebraic connections between this passive model order reduction algorithm and other Krylov space methods. In addition, a convergence criteria based on an error measure for PRIMA is presented as a first step towards intelligent order selection schemes. With these extensions and error criterion examples demonstrate that accurate approximations are possible well into the RF frequency range even with expansions about s=0.

A new discrete transmission line model for passive model order reduction and macromodeling of high-speed interconnections

A new, computationally efficient, discrete model is presented for passive model order reduction of high-speed interconnections. The proposed discrete model is based on the use of the theory of compact finite differences for the development of the discrete approximation to the transmission line equations that govern wave propagation on the interconnections. Thus result in a discrete model that utilizes only a few unknowns per wavelength and yet provides highly accurate waveform resolution. In addition to improved computational efficiency, the generated discrete model is passive, and compatible with the passive reduced-order interconnect modeling algorithm (PRIMA). Thus, it is suitable for the development of passive reduced-order models of interconnection networks of high complexity. Numerical experiments from the simulation and model order reduction of coupled interconnections are used to illustrate the validity and efficiency of the proposed model.

An all-purpose transmission-line model for interconnect simulation in SPICE

A new all-purpose multiconductor transmission-line model is described for efficient and robust interconnect simulation using nonlinear circuit simulators such as SPICE. All types of interconnects, i.e., uniform, nonuniform, lossless, lossy/dispersive, can be handled by the proposed model. Furthermore, coupling of electromagnetic radiation to interconnects can be directly modeled without the need for developing a new subcircuit. Another advantage of the proposed model is that it enables sensitivity analysis with respect to both circuit and interconnect parameters, thus facilitating interconnect circuit optimization. Chebyshev expansions for the spatial variations of the interconnect voltages and currents are used to effect highly accurate numerical approximations of the Telegraphers equations using as small a number of degrees of freedom as possible. A simple rule of thumb is provided for the selection of the order of the approximation given the frequency bandwidth of interest. Numerical examples are presented to demonstrate the validity of the proposed model and illustrate its application to a variety of interconnect-induced noise interactions in high-speed electronic systems.

S2P: a stable 2-pole RC delay and coupling noise metric [IC interconnects]

The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. However, for deep submicron technologies, the accuracy of the Elmore delay is insufficient. In this paper we formulate a delay model using a provably stable two pole waveform response that provides a unique mapping between four moments and a specific delay value. Unlike traditional moment matching, this two-pole model permits us to precharacterize the delays, and store them in a table, as a mapped function of three parameters. The model also provides an explicit expression for the peak noise induced on a coupled line as a function of the same three moments. The results indicate runtimes comparable to an Elmore delay calculation but with the accuracy of an AWE approximation.

Min/max on-chip inductance models and delay metrics

This paper proposes an analytical inductance extraction model for characterizing min/max values of typical on-chip global intercon-nect structures, and a corresponding delay metric that can be used to provide RLC delay prediction from physical geometries. The model extraction and analysis is efficient enough to be used within optimization and physical design exploration loops. The analytical min/max inductance approximations also provide insight into the effects caused by inductances.

Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees

As IC clock frequencies approach the GHz range, the distribution of the clock signals becomes more critical in terms of controlling both skew and signal attenuation. Moreover, inductance effects are evident since RC transmission lines will overly attenuate these high-frequency clock signals. To facilitate accurate optimization of clock tree performance and skew requires simple metrics which capture these high-frequency effects. In this paper, we derive simple metrics and bounds for the phase delay and the attenuation of a periodic [RC(L)] tree response as a function of the fundamental frequency of the clock signal. These metrics are based on the first two moments of the impulse response, and are shown to further provide a mechanism for control of underdamped responses (reflections). An important result of this work is the clear demonstration that once the attenuation of the clock signal is controlled, the phase delay can be accurately captured in terms of the first-moment. Furthermore, the form of these metrics and their relationship to one another provides an excellent foundation for various forms of clock tree optimization.

Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations

The large-scale process and environmental variations for todays nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective under large-scale variations and propose a novel sensitivity framework to assess the ldquocriticalityrdquo of every path, arc, and node in a statistical timing graph. We theoretically prove that the path sensitivity is exactly equal to the probability that a path is critical and that the arc (or node) sensitivity is exactly equal to the probability that an arc (or a node) sits on the critical path. An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industrial examples.