Yil-Suk Yang

Design of non-uniform 100-V super-junction trench power MOSFET with low on-resistance

The specific on-resistance of non-uniform super-junction (SJ) trench metal-oxide semiconductor field-effect transistor (TMOSFET) is superior to that of uniform SJ TMOSFET under the same breakdown voltage. For the desired blocking voltage with 100-V, the electric field varies exponentially with distance between the drain and the source regions. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The doping concentration linearly decreases in the vertical direction from the N drift region at the bottom to the channel one at the upper. The structure modeling and the characteristic analyses for doping density, potential distribution, and electric field are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on-resistance of 0.66 mΩ · cm2 at the class of 100 V and 100 A is successfully optimized in the non-uniform SJ TMOSFET, which has the better performance than the uniform SJ TMOSFET in the specific on-resistance.

Electrical characteristics of novel ESD protection devices for I/O and power clamp

This paper presents a novel silicon controlled rectifier (SCR)-based (Electrostatic Discharge) ESD protection devices for I/O clamp and power clamp. The proposed ESD protection devices has a high holding voltage and a low tigger voltage characteristic than conventional SCR. These characteristics enable to latch-up immune under normal operating conditions as well as superior full chip ESD protection. Also, the propsed devices can provide area efficiency in comparison to conventional (Gate Grounded NMOS) GGNMOS. The propsed devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) technology. From the experimental results, the device for Input/Output (I/O) clamp has a trigger voltage of 6.5V, 7.7V and 8.1V with the LG1 of 0.5um, 0.8um and 1um, respectively. And the device for power clamp has a holding voltage of 8V, 10V and 11.3V with the D1 of 4.5um, 5.5um and 7um. Also, the device for I/O clamp has trigger voltage of 7.8V to 8.9V with the gate length (LG1) of 0.5um, 0.8um and 1.0um. Moreover, The proposed devices have high ESD robustness.

Electrical characteristics of the novel BiCMOS ESD protection circuit with low trigger voltage, low leakage and fast turn-on

In this paper, electrostatic discharge (ESD) protection circuit with an advanced substrate-triggered NMOS and a gate-substrate triggered NMOS using PNP bipolar transistor are proposed to provide low trigger voltage, low leakage, and fast turn-on speed. The experimental result show that the proposed substrate-trigged NMOS has a low trigger voltage of 5.98V and faster turn-on time(∼37ns). The proposed gate-substrate NMOS has a lower trigger voltage of 5.31V and low leakage current of 80pA.

A Novel Fabrication of TDMOSFETs Using Two Steps Trench Etching and Twice Self-Alignment Technique

ABSTRACT A new fabrication method employing two-step trench etching and twice self-alignment technique was developed to obtain high cell density trench power MOSFETs by using only three mask steps. This method was implemented to increase cell density, to decrease on-resistance and to improve leakage current characteristics. The trench DMOSFETs with 1.6 μm cell pitch and 140 Mcell/in2 cell density were fabricated. The specific on-resistance of the device is about 0.48 mΩ˖cm2 with the breakdown voltage of 43 V.

High performance of PMSM driver IC integrated sensorless and current sensing circuits

This work proposes high performance of permanent-magnet synchronous motor (PMSM) driver IC integrated with position sensorless scheme and current sensing circuits. The position sensorless scheme is adapted with digital sliding mode observer (SMO) method that has high robust characteristics of motor parameter variations. For current sensing circuits, 10-bit successive approximation (SAR) analog-to-digital converters (ADC) and various (1~16) gain amplifiers are implemented in the fabricated IC. The proposed PMSM driver IC is fabricated with 0.18um BCD process. Compared with the commercial module, with the accurate SMO scheme, a speed error is reduced to 0.7% at 3000rpm and a system efficiency is increased to 1.9 % at 3000rpm, 5N·m. The high precision position estimating driver IC is achieved without any position/current sensors.

Esd Protection circuits with low triggering vlotage, low leakage current and fast turn-on

ESD Protection circuits with low triggering voltage, low leakage current and fast turn-on using trigger techniques are presented in this paper. The proposed ESD protection devices are designed in 0.13um CMOS Technology. The results show that the proposed substrate Triggered NMOS using bipolar transistor has a lower trigger voltage of 5.98V and a faster turn-on time of 37ns. And the results show that the proposed gate-substrate triggered NMOS have lower trigger voltage of 5.35V and lower leakage current of 80pA.