Jin-Gyun Chung

Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors

Memory references in digital signal processors (DSP) are expensive due to their long latencies and high power consumption. Implementing fast Fourier transform (FFT) algorithms on DSP involves many memory references to access butterfly inputs and twiddle factors. Conventional FFT implementations require redundant memory references to load identical twiddle factors for butterflies from different stages in the FFT diagrams. In this paper, we present novel memory reference reduction methods to minimize memory references due to twiddle factors for implementing various different FFT algorithms on DSP. The proposed methods first group the butterflies with identical twiddle factors from different stages in the FFT diagrams and compute them before computing other butterflies with different twiddle factors, and then reduce the number of twiddle factor lookups by taking advantage of the properties of twiddle factors. Consequently, each twiddle factor is loaded only once and the number of memory references due to twiddle factors can be minimized. We have applied the proposed methods to implement radix-2 DIF FFT algorithm on TI TMS320C64x DSP. Experimental results show the proposed methods can achieve average of 76.4% reduction in the number of memory references, 53.5% saving of memory spaces due to twiddle factors, and average of 36.5% reduction in the number of clock cycles to compute radix-2 DIF FFT on DSP comparing to the conventional implementation. Similar performance gain is reported for implementing radix-2 DIT FFT algorithms using the new methods

Low error fixed-width modified Booth multiplier

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with slight increase in the overhead of bias generation circuit.

Implementation of FlexRay communication controller protocol with application to a robot system

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung 0.35 mum technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

Implementation of FlexRay protocol with an automotive application

FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (specification and description language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system is synthesized using Samsung 0.35 muml technology. It is shown that the designed system can operate in the frequency range up to 76 MHz. In addition, the FlexRay system is implemented using ALTERA excalibur ARM EPXA4F672C3 with a bus driver chip AS8211. It is shown that the implemented system operates successfully in automobile advance alarm system in vehicle applications.

Power and Area Efficient Squarer Design

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present a high performance parallel squarer design method. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

Noise generation system using DCT

The performance of communication systems should be tested against a set of requirements. This procedure requires various noise sources to be connected onto the line to inject the specified noise signals into the receiver of the communication system. In this paper, a flexible noise generation algorithm using DCT is proposed. It is shown that the proposed method outperforms conventional methods when a noise model requires complicated PSD specifications.

Low-power FFT design for NC-OFDM in cognitive radio systems

Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as ‘0’. In this paper, based on the fact that there are many ‘0’ input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24 SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.

Efficient IFFT design using mapping method

FFT/IFFT processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the register size required for IFFT, we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the proposed IFFT design method achieves more than 60% area reduction and much SQNR (Signal-to-Quantization Noise Ration) gain compared with previous IFFT designs.

Automobile Advance Alarm System Based on Monocular Vision Processing

While the interests in intelligent vehicle increase, many people are having concerns about systems that offer the information of distance and relative speed between two cars. This paper presents an algorithm to obtain efficiently the distance between two cars.

Low power multi-channel capacitive touch sensing unit using capacitor to time conversion method

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and I2C for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 mm2.