In-Gul Jang

Low-power FFT design for NC-OFDM in cognitive radio systems

Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as ‘0’. In this paper, based on the fact that there are many ‘0’ input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24 SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.

Efficient IFFT design using mapping method

FFT/IFFT processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the register size required for IFFT, we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the proposed IFFT design method achieves more than 60% area reduction and much SQNR (Signal-to-Quantization Noise Ration) gain compared with previous IFFT designs.

Automobile Advance Alarm System Based on Monocular Vision Processing

While the interests in intelligent vehicle increase, many people are having concerns about systems that offer the information of distance and relative speed between two cars. This paper presents an algorithm to obtain efficiently the distance between two cars.

Design of FlexRay-MOST gateway using static segments and control messages

Due to the increasing requirements on the high speed communication and infotainment applications for automobiles, much research has been carried out for high speed automobile network technology called Media Oriented System Transport (MOST). Since many electronic control units (ECUs) are connected to the traditional automotive networks such as CAN, LIN and FlexRay, a network gateway is needed to bridge between MOST and other traditional networks. In this paper, we present a FlexRay-MOST gateway architecture. The proposed gateway system is designed with Verilog HDL and implemented using SoC kits.

Memory reduction of IFFT using CIM(combined integer mapping) for OFDM transmitters

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically (log2N) as the transform length (N) increases, the number of required registers (or, memories) increases linearly. In large transform length FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined integer mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 34.7% area reduction and 33.4% power reduction compared with conventional IFFT designs.

Memory reduction of IFFT using separated CIM (combined integer mapping) method

While the number of FFT stages increases logarithmically (log2N) as the transform length (N) increases, the number of required registers (or, memories) increases linearly. In large transform length FFT designs, the registers occupy more than 70% of the chip area. Recently, combined integer mapping (CIM) method was proposed to reduce the memory size of IFFT for OFDM transmitters. The CIM method focuses on reducing the memory size in the first two stages of the IFFT architectures since the first two stages require 75% of the total memory. In this paper, we propose separated CIM (SCIM) method to further reduce the memory size of IFFT. By SCIM method, real data and imaginary data are mapped differently. By simulations, it is shown that the proposed SCIM design method achieves more than 20% memory reduction compared with CIM method.

Interpolation circuit design for XRF systems using FFT

Interpolation circuits are widely used in many communication and digital signal processing systems. In this paper, we present a new interpolation algorithm to obtain the peak values of input waveforms in the shape of normal distribution curve used in XRF systems. Proposed algorithm is based on the combination of FFT and Lagrange interpolation method. In addition, optimized max value search algorithm and interpolation reduction algorithm are proposed for efficient hardware implementation. The performance of the proposed algorithm is verified using Verilog HDL.

A memory size reduction method of pipelined IFFT processor for OFDM systems

In this paper, we propose a new IFFT design method for orthogonal frequency division multiplexing (OFDM) systems to reduce the memory size of IFFT based on a combined integer mapping of three IFFT input signals: modulated data, pilot and null signals. The proposed method focuses on reducing the size of memory cells in the first two stages of the pipelined architectures since the first two stages require 75% of the total memory cells. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than about 35% reduction in gate count and about 34% reduction in power consumption compared with conventional IFFT design.

Weighted interpolation using supplementary filter

Interpolation filters are widely used in many communication and multimedia applications. Polynomial interpolation computes the coefficients of the polynomial according to the input information to obtain the interpolated value. Recently, FIR interpolation method using supplementary filters was proposed to improve the performances of polynomial interpolation methods. In this paper, we propose a weighted interpolation method using supplementary filter to further increase the performances of the interpolation filters. Examples and simulation results show that the proposed approach exhibits improved performances compared with the original supplementary filter-based interpolation method.