Kyung-Ju Cho

Low error fixed-width modified Booth multiplier

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with slight increase in the overhead of bias generation circuit.

Implementation of FlexRay communication controller protocol with application to a robot system

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. FlexRay communication controller (CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung 0.35 mum technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

Efficient design of modified Booth multipliers for predetermined coefficients

Some digital signal processing applications, such as FFTs, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-24 FFT, the area and power consumption can be reduced by 18% and 36%, respectively

Power and Area Efficient Squarer Design

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present a high performance parallel squarer design method. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

Low-error fixed-width squarer design

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.

Error bound reduction for fixed-width modified Booth multiplier

The maximum error has serious effect on the performance of fixed-width multipliers that receive W-bit inputs and produce W-bit products. In this paper, we analyze the error bound of fixed-width modified Booth multiplier. Then, we present a method that can be used to reduce the maximum error. By simulations, it is shown that the performance of the proposed fixed-width multiplier is pretty close to that of the multiplier with rounding scheme.

Design of low error fixed-width squarer

The paper presents a design method for a fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To compensate efficiently for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.

Constant multiplier design using specialized bit pattern adders

The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.

Sound Source Localization Method Using Region Selection

There are many applications that would be aided by the determination of the physical position and orientation of users. Some of the applications include service robots, video conference, intelligent living environments, security systems and speech separation for hands-free communication devices (Coen, 1998; Wax & Kailath, 1983; Mungamuru & Aarabi, 2004; Sasaki et al., 2006; Lv & Zhang 2008). As an example, without the information on the spatial location of users in a given environment, it would not be possible for a service robot to react naturally to the needs of the user. To localize a user, sound source localization techniques are widely used (Nakadai et al., 2000; Brandstein & Ward, 2001; Cheng & Wakefield, 2001; Sasaki et al., 2006). Sound localization is the process of determining the spatial location of a sound source based on multiple observations of the received sound signals. Current sound localization techniques are generally based upon the idea of computing the time difference of arrival (TDOA) information with microphone arrays (Knnapp & Cater, 1976; Brandstein & Silverman, 1997). An efficient method to obtain TDOA information between two signals is to compute the cross-correlation of the two signals. The computed correlation values give the point at which the two signals from separate microphones are at their maximum correlation. When only two isotropic (i.e., not directional as in the mammalian ear) microphones are used, the system experiences front-back confusion effect: the system has difficulty in determining whether the sound is originating from in front of or behind the system. A simple and efficient method to overcome this problem is to incorporate more microphones (Huang et al., 1999). Various weighting functions or pre-filters such as Roth, SCOT, PHAT, Eckart filter and HT can be used to increase the performance of time difference estimation (Knnapp & Cater, 1976). However, the performance improvement is achieved with the penalty of large power consumption and hardware overhead, which may not be suitable for the implementation of portable systems such as service robots. In this chapter, we propose an efficient sound source localization method under the assumption that three isotropic microphones are used to avoid the front-back confusion

Hardware Efficient QR Decomposition for GDFE

This paper presents a QR decomposition core by exploiting Givens rotation for the generalized decision feedback equalizer (GDFE). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining the fixed-width modified-Booth multiplier and two-stage method (coarse and fine stage), we design an efficient QR decomposition core. By simulations, it is shown that the proposed QR decomposition core can be a feasible solution for GDFE.