Jin Ho Lee

Characterization and Estimation of Solder-on-Pad Process for Fine-Pitch Applications

Popular solder-bumping mechanisms such as electroplating and stencil printing suffer from either high process costs or technical limitations. A low-cost solder-on-pad (SoP) process has been developed to meet the requirements of fine-pitch solder bumping. This paper focuses on the characterization and estimation of the SoP process. To form a solder bump without soldering defects, optimum process conditions should be carefully designed. A model to estimate the bump volume and predict the bump height is suggested. By optimizing the composition of solder paste material called solder-bump-maker, and by adjusting the process conditions, Sn-Ag-Cu solder bumps with different heights are obtained. The experiments and analysis to understand the impact of parameters were based on test vehicles with 80 μm pitch size. Then, the measured heights of solder bumps are compared with the model to see how they fit the estimation. Finally, a similar process has been conducted to test vehicles with pitch sizes of 150 and 40 μm, to confirm the scalability of the SoP process in different pitch sizes.

Characterization of 3D stacked high resistivity Si interposers with polymer TSV liners for 3D RF module

The material designs of the Si interposers are optimized for a 3D RF module. The high resistivity Si wafers are used for the Si interposer fabrication: 1,000 Ω·cm ~ 10,000 Ω·cm. To reduce the capacitance and mechanical stress between Cufilled TSV and Si substrate, a polyimide insulation layer is applied as a TSV liner. We designs several types of the transmission line structures and measures their electrical properties. For the 3D interconnection between the Si interposers, fluxing underfill material is developed and used as a pre-applied underfill for the thermocompression bonding process. With these optimizations of materials design of the Si interposers, the microstrip line shows the electrical loss of 0.065 dB/mm at 10 GHz, and the insertion loss of the vertical transition is 0.4 dB at 10 GHz.

Development of low contact resistance interconnection for display applications

This paper focuses on development of a low contact resistance interconnection for low temperature bonding applications. Alternative to conventional display interconnection mechanisms using anisotropic conductive film (ACF), solder and underfill method using low melting point Bi58-Sn solder is suggested. Solder bumping is carried out using a maskless Solder-on-Pad technology. An average bump height of 16.4μm with 80μm bump pitch is achieved by optimizing the solder paste material called Solder-Bump-Maker. The test vehicle with bumps is flip chip bonded with a top die using Fluxing underfill. In order to analyze the quality of the bonded interconnection, contact resistance was measured using the 4-point probe method, and a moisture absorption test was conducted in a 85°C/85% relative humidity condition for 100 hours. The contact resistance values before and after the reliability test show no significant difference, which demonstrates that the suggested interconnection is a robust joint with increased electrical performance.

Thermal and Electrical Designs of RF 3D Module Based on Si Interposers with Redundant TSVs

Thermal and electrical designs were performed to implement a 3D T/R (Transmit/Receive)-module based on the Si interposers. Two types of 3D module structures were compared with respect to the thermal performance and manufacturability. The FEM simulations were conducted to check the feasibility of the Si interposers as the heat spreader in the 3D module. Two kinds of sintered silver pastes having the advantage of low temperature process were considered as a TIM (Thermal Interface Material) for the 3D module. Test vehicles with the adhesives were prepared, and their thermal performances were measured under the condition of the DC power consumption of 28W. The vertical transitions with redundant TSVs and solder bumps were designed to increase the yield of the 3D module. The effects of the open failure of the redundant TSVs on the electrical performance of the vertical transitions were simulated.

Characterization of hybrid underfill for low-temperature process applicable to flexible substrate

As the interests in wearable devices are become growing, flexible substrates is being extensively investigated. In this study, new hybrid underfill for a low temperature process to create an electrical interconnection system on flexible substrate was studied. Hybrid underfill material is composed with underfill materials and 54Bi27In19Sn solder powder which has melting temperature at 83°C. For the stable chemical reaction, process temperature was set to 130°C. Hybrid underfill material has advantage of reducing processing step because the processing step such as solder joint formation, fluxing, cleaning, underfill step can proceed at a time. To optimize the wettability of solder powder, compositions and the ratio or the materials and processing conditions are controlled. By controlling the various conditions such as reductant and catalyst of hybrid underfill material, we optimize the low temperature process. As a result, solder joint is formed stably at a low temperature.

Flip-chip bonding processes with low volume SoP technology

In order to build solder bumps with a fine-pitch of 100 μm and 130 μm on PCB substrate, low volume solder on pad (LVSoP) technology using a maskless technology was developed for SAC305 solder with a high melting temperature of 220°C. For the LVSoP process, SBM (solder bump maker) material was newly developed. The solder bump maker (SBM) paste and its process were quantitatively optimized to get a uniform height of solder bumps which are almost equal to the height of solder resist. Differential scanning calorimetry (DSC), viscosity measurement and physical flowing of SBM paste were precisely investigated and analyzed during LVSoP processing for an understanding of chemo-rheological phenomena of SBM paste. The average height of solder bumps and their maximum and minimum values were 14.7, 18.3 and 12.0 μm, respectively. It is believed that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field. Flipchip bonding process between PCB substrate with low volume solder bumps and silicon device having the cupper pillars without solder caps was performed. As one of the key solution for fine pitch interconnection with Cu pillar for Flipchip bonding process, it is expected that LVSoP technology can be effectively used in semiconductor packaging.