Kang-Wook Lee

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.

Highly beneficial organic liner with extremely low Thermal stress for fine Cu-TSV in 3D-integration

The constructive role played by the Thermal-chemical vapor deposited (CVD) organic polyimide (PI) liner in the Cu-TSVs with diameter or width (φ) varying from 3 μm to 30 μm has been studied meticulously for its thermal stability, leakage current (LC), capacitance, TSV-chain resistance, stress absorbing ability, and the Si-lattice distortion arising from thermo-mechanical stress (TMS). The measured LC values for the CVD deposited PI liner is in the order of 10-13 to 10-15 A, which is on par with the value obtained for the conventional SiO2 liner. The extremely low modulus value of PI liner helps not only to reduce the amount of Cu extrusion, but also maintain an uniform Cu-extrusion. We were able to achieve a conformal deposition of PI liner even in φ = 3 μm via having the aspect ratio of 10 with the step coverage values of more than 0.8 (80%) at the TSV bottom corner. It was found that the d-space changing and thus the lattice stress is nearly five times smaller for the TSV with PI liner (~200 MPa) than for the TSV with SiO2 liner (~1000 MPa). Nearly zero-degradation of PI liner was confirmed from C1s, O1s, and N1s core-level x-ray photoelectron spectra taken before and after annealing at 400 °C. We obtained the resistance value of as low as 18 mΩ per 10 μm-width TSV with 500 nm-thick PI liner fabricated on 12-inch wafer.

Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice

Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 ?m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current?voltage (I?V) characteristics.

Mechanical Characteristics of Thin Die/Wafers in Three-Dimensional Large-Scale Integrated Systems

A thickness value of less than 50 μm for die/wafers is a must meet criteria in 3-D large-scale silicon device integration, in order to reduce interconnect lengths and resistive-capacitive delays. The mechanical properties of such ultra-thin die/wafers, namely, Youngs modulus, hardness, etc., with respect to 1) different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc.); 2) various wafer thicknesses (10, 20, 30, 40, 50, 100, and 200 μm); and 3) different wafer types (P/P+, P/P-, and wafers with internal-gettering layers) were investigated by using a nano-indenter. The mechanical characteristic data obtained for the thin die/wafers were well supported by their corresponding residual stress values (obtained by laser micro-Raman spectroscopy) and the crystal mis-orientation results (obtained via electron back-scatter diffraction). The chemically-mechanically polished ultrathin dies/wafers were found to be extremely good from the perspective of both mechanical strength and residual stress when compared to their counter parts fabricated by all other die thinning methods considered in this study.

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV

Effects of electro-less Ni layer as barrier/seed layers were evaluated for high reliable and low cost Cu TSVs. To electrically characterize the effectiveness of a Ni layer as barrier/seed layers for TSV application, we fabricated the trench MOS capacitor with 5μm dia. and 50μm depth TSV array. Via holes were successfully filled by Cu electro-plating by using Ni seed layer. To characterize the blocking property of the Ni layer to Cu diffusion, Cu atoms were intentionally diffused from Cu TSV by annealing at 300°C and 400°C. X-ray spectrometer (EDX) and C-t analysis results shows that Cu atoms not diffuse into t h e Si substrate via the Ni layer even after annealing at 400°C. The Ni barrier layer has good blocking properties compared to a PVD barrier layer.

Characterization of Vapor Deposited Polyimides and Process Integration with the Polymeric Liner for Via-Last/Backside-Via Cu-TSV Formation

Abstract A vapor deposited polyimide (PI) as a TSV (through-Si via) dielectric liner is studied for 3D integration based on via-last/backside-via processes. In this work, Kapton-H is employed for a candidate of the PI TSV liner. The leak current (~ 1×10 A/cm) of the vapor deposited PI is low, and in addition, the PI liner shows lower thermal mechanical stress than a SiO2 liner deposited by plasma CVD with TEOS. The etching rates of the vapor deposited PI formed on the via top, sidewall, and bottom are approximately 1,300, 400, and 1,000 nm/min, respectively, suggesting that the vapor deposited PIs can be applied to TSV liners for via-last/backside-via 3D integration.

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration

A 12-channel vertical cavity surface emitting laser (VCSEL) chip was heterogeneously self-assembled to a glass interposer wafer by liquid surface tension as a driving force. The size of the VCSEL chip was 0.35 mm wide and 3 mm long. From the square dummy chips having structurally similar periphery to the VCSEL, the step structure at the chip edge was found to be significantly dependent on the alignment accuracies. From the rectangular dummy chips having the same sizes to the long VCSEL, the tiny chips were precisely self-assembled with alignment accuracies within 2 μm even when they were manually placed on water droplets provided on host Si wafers. After self-assembly of the VCSEL chip and the subsequent thermal compression, the VCSEL was accurately positioned, successfully emitted 850-nm light, and exhibited no degradation of the I-V characteristics. This paper also presents our recent progress on the hybrid integration of chip-scale photonic devices with 3D/TSV technologies for optical interconnections.

Investigation of the Plasma Damage by Etching Process for TSV Formation in Via-last Backside-via 3D IC

We have investigated the effect of plasma damage in TSV formation on MOSFET characteristics to discuss the new antenna rule for the 3D IC design. An IC chip for evaluation was bonded to Si interposer with Cu/Sn microbumps at 280°C for 190 sec and thinned to 50-uf06dm thickness. Via holes through a Si substrate for TSV are formed by ICP-RIE at the backside surface of the IC chip. Diameter and number of via holes are 25 uf06dm and 1, 6, 11, and 21, respectively. These via holes interconnected the first metal which interconnect the gate metal of MOSFET fabricated on IC chip. We measured the Id-Vg characteristics of the MOSFET before and after via-holes formation. The measurement results show no significant change even after via-holes formation. It is indicated that the via-hole-etching process doesn’t affect MOSFET characteristics, because the gate capacitance of MOSFET is much smaller than parasitic capacitance of the first metal.