Jin-hyeok Choi

8.7 A 0.0047mm 2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of f REF to 1GHz

There continue to be efforts to develop methodologies for fully automated digital design of key analog building blocks. The phase-locked loop (PLL) is a block for which an all-digital implementation has been sought recently. There have been several approaches for fully synthesized digital PLLs [1–4] via gate-level implementation of a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Though automated layout has been achieved, the lock-range and phase-noise performance are subject to process variations. Critical performance-limiting blocks, such as the TDC and DCO, should be carefully designed with analog circuit simulators, diluting the inherent benefits of digital design. This work presents a highly programmable and synthesizable TDC- and DCO-less fractional-N PLL architecture, employing a phase-locked direct-digital synthesizer (PLDDS) driven by a free-running oscillator. The PLDDS design is specified entirely in a register-transfer level (RTL) hardware-description language (HDL) without any need for analog simulation.

Design and implementation of a mobile storage leveraging the DRAM interface

Storage I/O performance remains a key factor that determines the overall user experience of a computer system. This is especially true for mobile systems as users commonly browse and navigate through many high-quality pictures and video clips stored in their device. The appetite for more appealing user interface has continuously pushed the mobile storage interface speed up; emerging UFS 2.0 standard provisions a maximum bandwidth of as high as 1,200 MB/s. In this work, we propose, design, and implement a mobile storage architecture that leverages the high-speed DRAM interface for communication, thus substantially expanding the storage performance headroom. In order to effectively turn the existing DRAM interface into a storage interface, we design a new storage protocol that runs on top of the DRAM interface. Our protocol builds on a small host interface buffer structure mapped to the systems memory space. Based on this protocol, we develop and fabricate a storage controller chip that natively supports the LPDDR3 interface. We also develop a host software stack (Linux device driver and boot loader) and a host platform board. Finally we show the feasibility of our proposal by constructing a full Android system running on the developed storage device and platform. Our detailed evaluation shows that the proposed storage architecture has very low protocol handling overheads and compares favorably to a UFS 2.0 device. The proposed architecture obviates the need for implementing a separate host-side storage controller on a mobile CPU chip.