Jae-Wook Yoo

Set-level thermal management with package thermal design in digital TV application

Thermal resistance is the most important parameter in package selection of high power devices. However, lower thermal resistances means higher package cost, so it is not easy to adopt high cost package like cavity down packages or flip-chip packages just for the thermal characteristics. Therefore, set-level thermal management and optimal thermal guide should be done before selecting thermally enhanced packages because set-level thermal management can provide us various possibilities to get proper thermal budget. Moreover, set-level thermal management can be very powerful tool in case of digital TV application because its thermal environment is apparently different from JEDEC thermal standards (JESD51). This paper will introduce simulation methodology for optimal thermal design in set- level including package selection with experimental work in digital TV applications.

A Junction Temperature Reduction Technique for a Microprocessor Considering Temperature Coupled Leakage Power

Leakage power is emerging as a key challenge in IC design. Since leakage power has super-linear dependency on operating temperature, it becomes imperative to consider the thermal effects while optimizing leakage power. In this paper, an inter-simulation technique which accounts for leakage power and temperature variations is present. Integrating leakage model and coupled thermal-leakage simulations, the converged temperature and power distributions are achieved. In order to flatten the on chip temperature gradient, the revised floorplan design of a microprocessor is proposed. The on-chip temperature distributions are verified with measurement results using an infrared thermography method. The analysis results show that the realistic on-chip temperature distribution is a key for a precise estimation of leakage power. In addition, an important design implication is that the leakage power optimization problem has to be considered as a synthetic task considering logic organization, circuit parameters and chip floor plan.

Thermal Characterization of Multi Stack Packages Using Linear Superposition Method

As the mobile products have been developed, many devices of various functions should be packaged into the limited space. Therefore, stacking multi-packages is needed for small form factor. Compared with discrete packages, multi stack packages (MSP) can provide better solutions for power saving, EMI reduction, max frequency up-grade in spite of its higher cost, low test yield, poor quality assurance, and more complicated manufacturing process. But, stacking many packages in confined space has raised concerns related to heat dissipation, which has become one of the most serious problems in the design of MSP. Accordingly, a method to obtain Tj for each chip from the power inputs is needed. This is quite significant at the MSP promotion and design stage, though the temperature value would be changed by system environment. In this paper, a new approach to determine the junction temperatures of the MSP is proposed. The average temperature of the chips was calculated by RSM, and the temperature difference from the average temperature was calculated by linear superposition. Using this approach, one can calculate device junction temperatures simply and accurately