Jin-Ping Han

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV) , threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology.

Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

In this paper, it is shown empirically and through simulation that transistor mismatch due to random dopant fluctuation is a function of the well and halo design of the transistor, and that, contrary to conventional expectation, low-threshold transistors can have larger mismatch than higher threshold transistors. The complex dependence of mismatch on well and halo profiles suggests the need for the extension of the conventional Pelgrom approach to characterizing mismatch for a given technology and also suggests means of optimizing mismatch for analog applications. A set of screening criteria for mismatch data analysis are presented to verify that conclusions drawn from the standard deviation of a distribution may be properly applied.

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond J.-P. Han, T. Shimizu, L.-H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, A. Azuma, G. Yang, M. Eller, D. Jaeger, H. Zhuang, K. Miyashita, K. Stein, D. Nair, J.-H. Park, M. Hamaguchi, S. Kohler, D. Chanemougame, W. Li, K Kim, N. Kim, C. Wiedholz, S. Miyake, G. Tsutsui, H. van Meer, J. Liang, M. Ostermayr, J. Lian, M. Celik, R. Donaton, K. Barla, M.H. Na, Y. Goto, M. Sherony, F. Johnson, R. Wachnik, J. Sudijono,E. Kaste, R. Sampson, J.-H. Ku, A. Steegen, W. Neumueller Infineon Technologies, Renesas, IBM Microelectronics, STMicroelectronics, Toshiba America, GLOBALFOUNDRIES, Samsung Electronics, alliances at IBM SRDC, 2070 Rt 52, Hopewell Junction, NY12533; jh262@ieee.org,

High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.

NiSi Roughness on Embedded SiGe

. Introduction Ni silicide has been considered as promising salicide process in below 65nm CMOS technology due to low Rs and lower thermal budget than Co silicide. Recently embedded SiGe(eSiGe) process has been widely developed to enhance pFET performance by hole mobility improvement. However, Ni silicidation on eSiGe showes several issues that need to be solved. One of them is bad roughness in between Ni silicide and eSiGe interface. Interface roughness caused by non-uniform silicide thickness on eSiGe is very susceptible to junction leakage current in source/drain (S/D) area and should be well controlled as the ground rule shrinks down. In this study, effects of pre amorphization implantation (PAI) and in-situ Si capping on top of eSiGe were examined to improve Ni silicide interface roughness.