Daniel J. Jaeger

Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

Silicon-germanium is an alternative channel material for pMOS FETs at 32-nm node and beyond because of lower threshold voltage and higher channel mobility in high-k metal gate technology. However, gate-induced drain leakage (GIDL) is a major concern at low power technology nodes because of band-to-band and trap-assisted tunneling (TAT) due to reduced bandgap. Here, we have studied the GIDL dependence on temperature as well as drain and substrate bias. Experimental results and Technology computer-aided design (TCAD) simulations suggest that the mechanism responsible for GIDL during off state is mostly phonon-assisted band-to-band tunneling (BTBT) in the top SiGe layer near the drain surface and is further contributed by BTBT at the drain sidewall junction. Other GIDL mechanisms such as TAT at the extension/sidewall dominate for other drain, gate, and substrate bias voltages.

Effect of Germanium Preamorphization Implant on Performance and Gate-Induced Drain Leakage in SiGe Channel pFET

Silicon-germanium (SiGe) channel pMOSFET is considered as a replacement for silicon channel device for 32-nm node and beyond, because of its lower threshold voltage and higher channel mobility. Lower SiGe bandgap makes gate-induced drain leakage (GIDL) important for low leakage, high threshold voltage device designs. In this letter, the effect of prehalo/LDD Ge preamorphization implant (PAI) on GIDL and performance is investigated using experimental data and simulations. Results suggest that GIDL reduction of ~40% is achieved without Ge PAI and the total OFF-state leakage (IOFF) is reduced by ~50% with a slight reduction in drive current (ION) and similar short-channel effects as compared with the case with PAI for same process conditions, which is not reported yet. The reduction in GIDL, and hence the improvement in ION/IOFF ratio is because of elimination of end-of-range defects at the source/drain sidewall junction regions. It is also shown that a slight reduction in ION in the absence of Ge PAI is because of a small increase in the extrinsic series resistance.

Single wafer cleaning lessons in advanced node gate module development

With single wafer cleaning becoming a mature part of advanced semiconductor manufacturing, it seemed appropriate to reflect on a period of rapid and dramatic change within the gate module. Specifically, there are 6 key learnings that have enabled our team to take embedded contamination from top of the yield pareto to a more baseline level of defectivity. Those key learnings were: 1) Particle removal efficiency is critical. 2) DI Prewet improves pattern fidelity. 3) S/P ratio drives dual gate chemical oxide growth. 4) Hydrophobic dewetting can occur. 5) Predispense sequences are critical. 6) Concentration differences between batch and single wafer tooling can drive significant effects.

Leveraging puma DF wafer inspection to characterize root cause of yield loss on an advanced 32 nm HKMG SOI technology device

This paper presents a systematic methodology to enable Puma double dark field wafer inspection tool to detect key yield related defect that causes micro-masking defects in the Gate module/sector of an advanced 32nm High-K Metal Gate (HKMG) SOI technology device. Two approaches were adapted to detect the source of the micro-masking defect, namely (i) Patterned wafer inspection in High K metal Gate module to understand the initial findings (ii) Collaborative work with other advanced fabs (Partners) that led to a systematic partitioning approach through the Front End of the Line (FEOL) sectors to exactly pinpoint the root cause of the yield loss in Gate sector. Based on the above systematic partitioning approach, the source of the embedded defect that causes yield loss in gate sector was successfully identified. This methodology has also enabled a process fix to be put in place for reducing the addition of embedded defects in the FEOL sector and has directly helped in improving the yield in FEOL sector. This paper also discusses the advantage of collaborating with different wafer manufacturing companies (IBM partners) in being able to successfully identify root cause of key yield limiting issues.

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond J.-P. Han, T. Shimizu, L.-H. Pan, M. Voelker, C. Bernicot, F. Arnaud, A. C. Mocuta, K. Stahrenberg, A. Azuma, G. Yang, M. Eller, D. Jaeger, H. Zhuang, K. Miyashita, K. Stein, D. Nair, J.-H. Park, M. Hamaguchi, S. Kohler, D. Chanemougame, W. Li, K Kim, N. Kim, C. Wiedholz, S. Miyake, G. Tsutsui, H. van Meer, J. Liang, M. Ostermayr, J. Lian, M. Celik, R. Donaton, K. Barla, M.H. Na, Y. Goto, M. Sherony, F. Johnson, R. Wachnik, J. Sudijono,E. Kaste, R. Sampson, J.-H. Ku, A. Steegen, W. Neumueller Infineon Technologies, Renesas, IBM Microelectronics, STMicroelectronics, Toshiba America, GLOBALFOUNDRIES, Samsung Electronics, alliances at IBM SRDC, 2070 Rt 52, Hopewell Junction, NY12533; jh262@ieee.org,

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

For the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.