Jin-Sheng Wang

A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter

This paper presents a high-speed high-resolution low-power CMOS switched-current cyclic analog-to-digital converter (ADC). The high performance is attributed to the use of the following components: (1) a high-performance residual amplifier which takes two clock cycles to double a current; and (2) an efficient cyclic redundant signed-digit algorithm which provides 1.5 bit resolution without using two matched reference currents. Simulation results show that the developed ADC achieves 12-bit resolution and a conversion rate of 100 ns/bit, where the low-cost MOSIS SCAN20 2 /spl mu/m CMOS process and 3.3 V supply voltage are employed. The converter has been fabricated and tested, Experimental results on the test chip are also presented. The test chip achieves 12 bit resolution with differential nonlinearity of 0.6 LSB and the integral nonlinearity of 0.5 LSB when operated at a 0.8 Msample/s conversion rate. The power consumption is 1.9 mW.

Accurate CMOS switched-current divider circuits

This paper presents a highly accurate current divider using switched-current (SI) technique. The circuit accurately divides an input current by two with 3 cycles at each iteration. The accuracy of the division increases as the number of iterations increases. In practice, however, the accuracy is limited due to the clock-feedthrough errors. The issue of accuracy limitation is addressed. The extension to array structures for low-power/low-voltage A/D and D/A converter circuit designs is also discussed.

Design and analysis of high performance current reference generators for low-power CMOS data converters

Based on a highly accurate current divider using switched current technique without the need of well-matched components, a current reference generator (CRG) circuit is developed to generate and hold the weighed currents used in the data converters. This paper also presents a methodology for designing high-performance CMOS CRG circuits for low-power applications and their performance analysis for estimating the accuracy, speed, and power consumption. To demonstrate the design procedure and performance analysis, several design examples are given. The simulation results show that, for a 6-bit CRG circuit, its calibration time and holding time are 27 and 242 /spl mu/s, respectively, and for a 8-bit CRG circuit, they are 48 and 236 /spl mu/s, respectively. The circuit consumes 1.8 mW and achieves better than 10-bit accuracy, where a MOSIS SCNA20 2-/spl mu/m process and a 3.3-V supply voltage are employed. Thus, the developed CRG circuit is well suited for low-power/low-voltage and moderate resolution data converters.

A 10-b, 100 MS/s, 2.8 mW CMOS switched-current DAC for low-power/low-voltage signal processing applications

This paper presents a CMOS switched-current DAC (Digital-to-Analog Converter) circuit which achieves 10-bit resolution, 100 M samples per second conversion rate, and consumes 2.8 mW for 3.3 V power supply voltage, where MOSIS SCNA20 2 /spl mu/m process is employed. The developed DAC circuit employs a 7-bit multiply-by-two circuit and a 3-bit divide-by-two circuit to simultaneously generate 10 weighted currents. Results show that the developed converter circuit is well suited for low-power/low-voltage signal processing applications.

High-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications

This paper presents a CMOS switched-current D/A (digital-to-analog) converter circuit which achieves 10-bit resolution, 100 MSamples per second conversion rate, and consumes 2.3 mW, where MOSIS SCNA20 2 /spl mu/m process and 3.3 V supply voltage were simulated. The developed D/A converter circuit generates 10 weighted currents using a 7-bit current multiplier circuit and a 3-bit current divider circuit. Results show that the converter circuit is well suited for low-power/low-voltage signal processing applications.

Fault simulation of built-in tester for CMOS switched-current circuits

This paper presents a built-in tester that enhances the testability of CMOS switched-current circuits and simplifies their test generation process. The tester is comprised of a high accuracy current comparator, a voltage winder comparator, and a digital latch. In this study, a high accuracy current comparator which is capable of autozeroing and self-testing is developed. The autozeroing property increases the accuracy of the tester. This paper demonstrates the self-testability of the tester through a fault simulation.

Synthesis of optimal current copiers for low-power/low-voltage switched-current circuits

This paper deals with the noise issue of current copiers. It introduces a structure function for a current copier to estimate its SNR (signal-to-noise ratio). Different copiers have different structure functions. A current copier with a higher structure function value has the larger SNR. This paper also defines the figure-of-merit (FOM), a performance measure, for various current copiers in terms of SNR, power dissipation, settling time, and the storage capacitance. Several current copiers are compared with their FOMs. Based on the desired FOM, this synthesis process provides the designers with the optimum transistor size and storage capacitor for the selected current copier.

A fully differential switched-current ADC with improved performance

This paper presents a new current copier which uses a differential-pair as its storage cell. The differential-pair storage unit (DPSU) significantly reduces clock-feedthrough errors and achieves high linearity, large dynamic range, and less cross-talk noise. The high performance DPSU can be used to designed a fully differential switched-current ADC to improve performance.

A fully differential current copier for performance improvement

This paper presents a new current copier which uses a differential-pair as its storage cell. The differential-pair storage unit (DPSU) significantly reduces clock-feedthrough errors and achieves high linearity, large dynamic range, and less cross-talk noise. Therefore, the proposed high-performance DPSU can be used to improve the speed performance of analog-to-digital converters which implement the proposed fully differential switched-current technique.

A 12-b, 100 ns/b, 1.9 mW switched-current cyclic A/D converter

This paper presents a high-speed, high-resolution, and low-power CMOS switched-current cyclic Analog-to-Digital Converter (ADC). The high performance is attributed to the use of the following components: (1) a high-performance residual amplifier which takes two clock cycles to double a current; and (2) an efficient cyclic RSD algorithm which provides 1.5 b resolution without using two matched reference currents. Simulation results show that the developed ADC achieves 12-bit resolution, a conversion rate of 100 ns per bit, and a power consumption of 1.9 mW, where the low-cost MOSIS SCAN20 2 /spl mu/m CMOS process and 3.3 V supply voltage are employed.