Renyuan Huang

Design of high-speed high-accuracy current copiers for low-voltage analog signal processing applications

For high-accuracy current-mode circuits, their basic building blocks, current copiers, determine their speed and accuracy. A current copier suffers from two major error effects which are due to nonzero output conductance and clock feedthrough. This brief presents a simple current copier with a negative-feedback structure to alleviate the error due to nonzero output conductance, where the feedback amplifier is implemented by a bipolar inverter with high voltage gain and large bandwidth. This brief also presents the design constraints and trade-off for reducing the error due to the clock feedthrough. The PSPICE simulation results show that the copier achieves an accuracy of more than 10 b with a settling time within 6 ns for the input currents ranged from 0.5 to 3 mA, where a power supply of 3.3 V and a 2 /spl mu/m BiCMOS process are assumed. Thus, this current copier is well suited to the high-accuracy high-speed and low-voltage analog signal processing applications.

Simple yet accurate current copiers for low-voltage current-mode signal-processing applications

As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5 V, current-mode signal-processing techniques will surely become increasingly important and attractive. Numerous current copiers have been proposed. Among them, the copier with a negative feedback approach is the best candidate for low-voltage current-mode signal-processing applications. However, the copier using a positive-gain feedback amplifier achieves better accuracy at the cost of increasing circuit complexity and settling time. This paper presents an alternative circuit implementation of the negative feedback approach. The proposed current copier uses a negative-gain feedback amplifier which can be easily realized by a simple circuitry with high accuracy and faster settling time. Simulation results show that with the simple digital CMOS process the proposed copier can be realized with only three transistors, achieves a dynamic range from 300 to 550 μA with an accuracy of 0.1% and can be settled within 3 ns with a power supply of 3.3 V. Thus the copier is well suited to our low-voltage current-mode sensor array applications

A 5 mW, 12-b, 50 ns/b switched-current cyclic A/D converter

This paper presents a high-speed, high-resolution and low-power switched-current cyclic A/D converter. The high performance is attributed to: (1) the use of high-performance current copiers; (2) the use of a high-performance residual amplifier which takes two clock cycles to double a current; (3) the use of an efficient cyclic RSD algorithm which provides 1.5 b resolution without using two matched reference currents.

A high-accuracy CMOS oversampling switched-current sample/hold (S/H) circuit using feedforward approach

This brief presents a CMOS oversampling current sample/hold (S/H) circuit using feedforward approach. The circuit adopts an integrating feedback structure which reduces the possible errors of the current copier used to sample the input current, due to clock feedthrough, channel-length modulation and capacitive feedback. The feedforward significantly reduces the output swing of the integrator and thus improves the stability and accuracy of the circuit. As a result, high accuracy is obtained with only first-order integration and a low oversampling ratio, and the useful bandwidth is enlarged. Simulation results show a 90-dB signal-to-distortion ratio, which is more than 20-dB improvement over a simple current copier, where the SCDN20 2-/spl mu/m CMOS process and 3.3-V supply voltage are assumed.

A high-accuracy CMOS oversampling current sample/hold (S/H) circuit using feedforward approach

This paper presents a CMOS oversampling current sample/hold (S/H) circuit using a feedforward approach. The circuit is comprised of a switched-current integrator, a gain stage, and a current copier. The feedforward approach reduces the output swing of the integrator significantly, thus improving the stability and accuracy of the S/H circuit. The high accuracy is obtained with only one-order integration and a low oversampling ratio. Results show that the circuit can reach 60 dB signal-to-distortion (SDR) ratio with a signal bandwidth of 2 MHz, where the SCAN20 2 /spl mu/m CMOS process and a 3.3 supply voltage are used.

Synthesis of optimal current copiers for low-power/low-voltage switched-current circuits

This paper deals with the noise issue of current copiers. It introduces a structure function for a current copier to estimate its SNR (signal-to-noise ratio). Different copiers have different structure functions. A current copier with a higher structure function value has the larger SNR. This paper also defines the figure-of-merit (FOM), a performance measure, for various current copiers in terms of SNR, power dissipation, settling time, and the storage capacitance. Several current copiers are compared with their FOMs. Based on the desired FOM, this synthesis process provides the designers with the optimum transistor size and storage capacitor for the selected current copier.

A fully differential switched-current ADC with improved performance

This paper presents a new current copier which uses a differential-pair as its storage cell. The differential-pair storage unit (DPSU) significantly reduces clock-feedthrough errors and achieves high linearity, large dynamic range, and less cross-talk noise. The high performance DPSU can be used to designed a fully differential switched-current ADC to improve performance.

A fully differential current copier for performance improvement

This paper presents a new current copier which uses a differential-pair as its storage cell. The differential-pair storage unit (DPSU) significantly reduces clock-feedthrough errors and achieves high linearity, large dynamic range, and less cross-talk noise. Therefore, the proposed high-performance DPSU can be used to improve the speed performance of analog-to-digital converters which implement the proposed fully differential switched-current technique.

Design of high-accuracy CMOS oversampling current sample/hold (S/H) circuits

This paper presents a CMOS oversampling current sample/hold (S/H) circuit using feedforward approach. The circuit adopts an integrating feedback structure which reduces the possible errors of the current copier used to sample the input current, due to clock feedthrough, channel-length modulation and capacitive feedback. The feedforward significantly reduces the output swing of the integrator and thus improve the stability and accuracy of the circuit. As a result, high accuracy is obtained with only first-order integration and a low oversampling ratio, and the useful bandwidth is enlarged. Simulation results show a 90 dB signal-to-distortion ratio, which is more than 20 dB improvement over a simple current copier, where the SCDN20 2 /spl mu/m CMOS process and 3.3 V supply voltage are assumed.