Jincheol Yoo

Fat tree encoder design for ultra-high speed flash A/D converters

The thermometer code-to-binary code encoder has become the bottleneck of ultra-high speed flash ADCs. In this paper, the authors present the fat tree thermometer code-to-binary code encoder that is highly suitable for ultra-high speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder is an effective solution for the bottleneck problem in ultra-high speed ADCs.

A 1-GSPS CMOS flash A/D converter for system-on-chip applications

This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 /spl mu/m standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013 mm/sup 2/ area. The proposed A/D converter is suitable for System-on-Chip (SoC) applications in wireless products and other ultra high speed applications.

A power and resolution adaptive flash analog-to-digital converter

A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 μm CMOS technology. The PRA-ADC design is applicable to RF portable communication devices, allowing tighter management of power and efficiency.

Design method and automation of comparator generation for flash A/D converter

The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.

Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter

This paper presents a comparator generation and selection method to reduce the linearity errors—DNL and INL—for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2n − 1 comparators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different sizes to provide internal reference voltages, while the differential comparators have identical sizes. The design method has been incorporated into a software package and the 2n − 1 optimized TIQ comparator layouts are generated as an output of the software package. The linearity errors against the CMOS process, power supply voltage, and temperature variations are significantly improved by the proposed comparator generation and selection method for the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation can be almost eliminated. The simulation results show 82.6% of DNL and 32.5% of INL improvements against CMOS process variation. For the other variations—power supply voltage and temperature—43.5% for DNL and 6.0% for INL improvement has been achieved. The prototype chips have been fabricated and the chip test results confirms the simulation results.

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications

Design and performance of an ultrafast 8bit 0.25 /spl mu/m CMOS flash ADC based on the thresholding inverter comparator are presented.

A high-speed power and resolution adaptive flash analog-to-digital converter

A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 /spl mu/m and 0.07 /spl mu/m CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

CMOS flash analog-to-digital converter for high speed and low voltage applications

A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A fat tree encoder that has signal delay of O(log2 N) is used for performance. A 6-bit and an 8-bit flash ADC were designed with 0.07 mµ CMOS technology and 0.7 V power supply voltage. The 6-bit ADC operates up to 4.76 giga samples per second (GSPS) with 11.35 mW power consumption. In case of the 8-bit ADC, it consumes 48.90 mW at its high speed 3.57 GSPS.

Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters

This paper presents a new voltage comparator design called Quantum Voltage (QV) comparator for the next generation deep sub-micron low voltage CMOS flash A/D converter (ADC). Unlike the traditional differential voltage comparators designed to minimize input-offset voltage error due to the mismatches in a differential transistor pair the QV comparators are designed to optimize the input-offset voltages by systematically and uniformly varying the transistor sizes of the differential transistor pair. The QV comparators allow very small voltage comparison, complete elimination of resistor ladder circuit, and dramatic improvement of linearity in an ADC.

Highly Efficient Comparator Design Automation for TIQ Flash A/D Converter

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.