Kyusun Choi

“The CMOS Inverter” as a Comparator in ADC Designs

This paper introduces a single-ended non-offset-cancelled flash ADC architecture, the “Threshold Inverter Quantizer” (TIQ). The TIQ is based on a CMOS inverter cell, in which the voltage transfer characteristics (VTC) are changed by systematic transistor sizing. As a result, a significant improvement of speed and reduction of area and power consumption is achieved. A sample TIQ based flash ADC chip including 3-bit, 4-bit and 6-bit versions together has been designed and fabricated with the 2 μ standard CMOS n-well technology. The proposed ADC cells are suitable for System-on-Chip (SoC) applications in high speed wireless products.

Fat tree encoder design for ultra-high speed flash A/D converters

The thermometer code-to-binary code encoder has become the bottleneck of ultra-high speed flash ADCs. In this paper, the authors present the fat tree thermometer code-to-binary code encoder that is highly suitable for ultra-high speed flash ADCs. The simulation and the implementation results show that the fat tree encoder outperforms the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder is an effective solution for the bottleneck problem in ultra-high speed ADCs.

A 1-GSPS CMOS flash A/D converter for system-on-chip applications

This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 /spl mu/m standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013 mm/sup 2/ area. The proposed A/D converter is suitable for System-on-Chip (SoC) applications in wireless products and other ultra high speed applications.

High frequency piezoelectric MEMS ultrasound transducers

High-frequency ultrasound array transducers using piezoelectric thin films on larger structures are being developed for high-resolution imaging systems. The increase in resolution is achieved by a simultaneous increase in operating frequency (30 MHz to about 1 GHz) and close coupling of the electronic circuitry. Two different processing methods were explored to fabricate array transducers. In one implementation, a xylophone bar transducer was prototyped, using thin film PbZr0.52Ti0.48O3 (PZT) as the active piezoelectric layer. In the other, the piezoelectric transducer was prepared by mist deposition of PZT films over electroplated Ni posts. Because the PZT films are excited through the film thickness, the drive voltages of these transducers are low, and close coupling of the electronic circuitry is possible. A complementary metal-oxide-semiconductor (CMOS) transceiver chip for a 16-element array was fabricated in 0.35-mum process technology. The ultrasound front-end chip contains beam-forming electronics, receiver circuitry, and analog-to-digital converters with 3-Kbyte on-chip buffer memory.

A power and resolution adaptive flash analog-to-digital converter

A new power and resolution adaptive flash ADC, named PRA-ADC, is proposed. The PRA-ADC enables exponential power reduction with linear resolution reduction. Unused parallel voltage comparators are switched to standby mode. The voltage comparators consume only the leakage power during the standby mode. The PRA-ADC, capable of operating at 5-bit, 6-bit, 7-bit, and 8-bit precision, dissipates 69 mW at 5-bit and 435 mW at 8-bit. The PRA-ADC was designed and simulated with 0.18 μm CMOS technology. The PRA-ADC design is applicable to RF portable communication devices, allowing tighter management of power and efficiency.

Design method and automation of comparator generation for flash A/D converter

The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ) based A/D converters require 2/sup n/ - 1 comparators, each one different from all others. Optimal design method of the TIQ comparator presented in this paper significantly improves the linearity of the A/D converter against the CMOS process variation. Especially the DNL dependence on the CMOS process variation can be almost eliminated. The design method has been incorporated into a software package and the 2/sup n/ - 1 optimized TIQ comparator layouts are generated as an output of the software package. The simulation results are presented to show the effectiveness of the design methods. Also, the prototype chip has been fabricated, with initial test results confirming the DNL reduction.

CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems

The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A prototype chip containing 16 receive and transmit channels with preamplifiers, time-gain compensation amplifiers, a multiplexed analog-to-digital converter with 3 kB of on-chip SRAM, and 50-MHz resolution time delayed excitation pulse generators has been fabricated. By utilizing a shared A/D converter architecture, the number of A/D converter and SRAM is cut down to one, unlike typical digital beamforming systems which need 16 A/D converters for 16 receive channels. The chip was fabricated in a 0.35-mum standard CMOS process. The chip size is 10 mm2, and its average power consumption in receive mode is approximately 270 mW with a 3.3-V power supply. The transceiver chip specifications and designs are described, as well as measured results of each transceiver component and initial pulse-echo experimental results are presented.

Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter

This paper presents a comparator generation and selection method to reduce the linearity errors—DNL and INL—for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2n − 1 comparators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different sizes to provide internal reference voltages, while the differential comparators have identical sizes. The design method has been incorporated into a software package and the 2n − 1 optimized TIQ comparator layouts are generated as an output of the software package. The linearity errors against the CMOS process, power supply voltage, and temperature variations are significantly improved by the proposed comparator generation and selection method for the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation can be almost eliminated. The simulation results show 82.6% of DNL and 32.5% of INL improvements against CMOS process variation. For the other variations—power supply voltage and temperature—43.5% for DNL and 6.0% for INL improvement has been achieved. The prototype chips have been fabricated and the chip test results confirms the simulation results.

VLSI implementation of a 256*256 crossbar interconnection network

Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. The paper presents the analysis of VLSI layout size and signal delay of the previous crossbar circuits. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256*256 crossbar on a 1cm/sup 2/ CMOS VLSI chip.<<ETX>>

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications

Design and performance of an ultrafast 8bit 0.25 /spl mu/m CMOS flash ADC based on the thresholding inverter comparator are presented.