Jingang Wu

Investigation of groove surface induced by strain relaxation in selective epitaxy SiGe process

Embedded SiGe or SiGe:B (e-SiGe or e-SiGe:B) PMOS source/drain (S/D) is widely used in advanced CMOS technology. However, with germanium (Ge) content increase, it becomes more and more challenging and critical to control defect and stress relaxation. In the present work, a groove-like surface defect of selective epitaxy SiGe was reported, which can be observed both on blanket wafer and device wafer. The groove-like defect induces very high junction leakage when this e-SiGe process applied in device wafer fabrication. Experimental results show both lattice mismatch and thermal mismatch induce strain relaxation which contributes to this specific surface defect. Two countermeasures were applied to fix these mismatch as well as surface defect, i.e. inserting a buffer layer of Si1-xGex or reducing the temperature difference among the different stack layers.

Investigation of Ni-based silicide formation by different dynamic surface annealing approaches

Sub-melt millisecond anneal (MSA) is one of major anneal techniques for forming ultra-shallow and highly activated junctions. Besides post-implant anneal for source/drain and source/drain extensions, MSA has also attracted increased interests in nickel-silicide formation recently. During the silicidation process, desired Ni diffusion in forming silicides is competing with un-wanted Ni diffusion along defects paths. The latter will cause higher junction leakage and/or source/drain leakage. Since the activation energy for the un-wanted diffusion is lower, higher process temperature with shorter duration is beneficial for minimizing the un-wanted diffusion. Furthermore, MSA allows high process temperature to be used for silicide formation, which can re-activate some dopants, such as arsenic and phosphors. These dopants are easily deactivated during lower temperature thermal processes post source/drain formation such as silicide block film deposition; therefore, transistor performance can be improved by using MSA for silicidation processes. In this work, dynamic surface annealing (DSA), which is one form of MSA techniques, was applied to form Ni-based silicides. The impacts of different combinations of soak RTA and DSA for thermal steps before and after selective nickel/NiSi strip were examined. One step DSA has been demonstrated effective reduction of Nickel piping by e-beam inspection count, improved NiSi resistance and junction leakage w/o device performance degradation.

Process match between DSA and LSA for ultra-shallow junction formation

Laser anneal (LA) is one of major millisecond anneal techniques (MSA) for forming ultra-shallow and highly activated junctions. There are two major commercially available laser anneal systems which are called laser spike annealing (LSA) and dynamic surface annealing (DSA) respectively. LSA and DSA are quite different in terms of laser source, wavelength, scanning mode and so on, their hardware and process specifications are definitely distinct from each other. In this work, the process match between DSA and LSA for ultra-shallow junction formation was studied using implanted blanket wafers as well as 45nm logic device wafers. It was found that through some process tuning knobs adjustments, such as peak temperature, dwell time, DSA can match LSA thermal budget well.

Device performance improvement with implantation balancing energy contamination and productivity

Ion implantation technology is widely used in semiconductor manufacturing process. Most of install base for high current implanters use deceleration technology to overcome space charge effect especially important for low energy implants. It is necessary to consider the Energy contamination (EC) effects on devices with thinner gate height. This paper use SRIM simulation and dopant profiles, offline sheet resistance to illustrate the selection of deceleration by considering EC tails beyond the gate height. The device effects using p-type Poly (PPoly) and Source Drain (PSD) implant steps are evaluated in state of art 28nm device flow. The device performance can gain 6% with optimized implant conditions. It demonstrated the necessary of balance device requirement and productivity using implanters with deceleration technologies. The newer generation implanters with EC filter technology, providing maximum productivity while meeting device requirement, was discussed briefly also.

Investigation of seal nitride process in 32nm beyond HK/MG technology

Seal nitride process of High-k/Metal Gate (HK/MG) technology is developed from offset nitride process of Poly/SiON technology which is widely used to define the source/drain extension area for overlap capacitor reduction and boron diffusion control of short channel effect improvement. In HK/MG technology era, the seal nitride process becomes more critical than Poly/SiON because the dummy poly will be removed in MG last process. The seal nitride process will not only be used to reduce overlap capacitance, short channel effect improvement, but also the seal nitride height impacts the metal gate electrode height for performance improvement which is retained after lightly doped drain, spacer formation process, etc. In this paper, the comparison between conventional nitride process and in-situ carbon doped seal nitride process is developed to prevent boron diffusion for better short channel effect control, also the process is developed to achieve lower wet etch rate for better critical dimension retention of lightly doped drain implantation control, metal height control after dummy poly removal. A different carbon concentration process is further developed after process tuning with the film characterization of wet etch rate, XPS measurement of impurity components, SIMS for carbon profile check and the electrical data is demonstrated to prove the performance gain.

Investigation of Si Implantation into ILD (Interlayer Dielectric) for film property modification

In this paper, a specific Si ion implantation is investigated as applied to ILD (Interlayer Dielectric) films (include SiO2 and SiN) property modification. The etch rate change of the films before/post implantation were checked by dilute HF solution and F radical contain plasma gas (SiCoNi@AMAT™). Different implant energy and dosage were also studied. It is found the etch rate of oxide and SiN films by dilute HF are both reduced dramatically after Si implantation, while etch rate as collected in SiCoNi chamber is varied by implant dosage. The as implanted Si profiles in dielectric films were checked by SIMS, which are consistent with the DHF wet etch rate (WER) change along the film surface to bulk. We also applied this Si implantation on HK/MG last CMOS device manufacture flow, the cross-section TEM results of pattern wafers confirm that it can obviously reduce the ILD films loss during dummy poly and oxide remove process.

Investigation of different post HK annealing impact on HK film property and device performance

HfO2 based high-permittivity gate dielectric has been introduced to CMOS logic device manufacturing since from 45nm node. However, these dielectrics are still under investigation and continuous optimization because of their relatively high oxygen vacancy concentration. Post Dielectric Annealing (PDA) after HK film may be a promising approach to reduce HK film trapped defect density and improve device performance as some literature reported recently. In the present work, different annealing conditions were applied on interface layer (IL)/HfO2 stack films, including soak annealing, spike annealing, and flash lamp based Milli-Second Annealing (MSA). Both blanket wafer and MOSCAP wafer characterization results show post HK MSA is an effective method to repair HK intrinsic defect, like oxygen vacancy, while it also beneficial for improving the Si/IL, IL/HK interface quality.

Investigation of nitrogen and carbon co-implantation under room temperature and cryo-condition

Co-implantation of non-dopant species is widely used in 65nm and beyond Complementary Metal-Oxide-Semiconductor (CMOS) technology node to meet ITRS ultra shallow junction roadmap and device performance requirement. With co-implantation, non-dopant species, such as Carbon (C), Fluorine (F) and Nitrogen (N), can either suppress doping diffusion or modify material property and improve device reliability. Cold implantation with wafer pedestal cooling to near −100°C is another hot topic in CMOS manufacture recently. It has obvious benefits, such as good amorphization performance, less end of range defect, less stress relaxation especially for e-SiGe formation. In the present work, different co-implantations with nitrogen and/or carbon were investigated for advanced NMOS Lightly Doped Drain (LDD) junction formation. The co-implantation was performed under room temperature or −100°C. It was found that C or C plus N co-implantations are very effective to suppress the diffusion of halo-implanted boron. Comparing with room temperature, the cryo-implantation under −100°C can get much better amorphization and less End of Range (EOR) defects, which result in reduced junction leakage and high activation as observed on blanket wafer and device wafers.