Yonggen He

Investigation of groove surface induced by strain relaxation in selective epitaxy SiGe process

Embedded SiGe or SiGe:B (e-SiGe or e-SiGe:B) PMOS source/drain (S/D) is widely used in advanced CMOS technology. However, with germanium (Ge) content increase, it becomes more and more challenging and critical to control defect and stress relaxation. In the present work, a groove-like surface defect of selective epitaxy SiGe was reported, which can be observed both on blanket wafer and device wafer. The groove-like defect induces very high junction leakage when this e-SiGe process applied in device wafer fabrication. Experimental results show both lattice mismatch and thermal mismatch induce strain relaxation which contributes to this specific surface defect. Two countermeasures were applied to fix these mismatch as well as surface defect, i.e. inserting a buffer layer of Si1-xGex or reducing the temperature difference among the different stack layers.

Investigation of Ni-based silicide formation by different dynamic surface annealing approaches

Sub-melt millisecond anneal (MSA) is one of major anneal techniques for forming ultra-shallow and highly activated junctions. Besides post-implant anneal for source/drain and source/drain extensions, MSA has also attracted increased interests in nickel-silicide formation recently. During the silicidation process, desired Ni diffusion in forming silicides is competing with un-wanted Ni diffusion along defects paths. The latter will cause higher junction leakage and/or source/drain leakage. Since the activation energy for the un-wanted diffusion is lower, higher process temperature with shorter duration is beneficial for minimizing the un-wanted diffusion. Furthermore, MSA allows high process temperature to be used for silicide formation, which can re-activate some dopants, such as arsenic and phosphors. These dopants are easily deactivated during lower temperature thermal processes post source/drain formation such as silicide block film deposition; therefore, transistor performance can be improved by using MSA for silicidation processes. In this work, dynamic surface annealing (DSA), which is one form of MSA techniques, was applied to form Ni-based silicides. The impacts of different combinations of soak RTA and DSA for thermal steps before and after selective nickel/NiSi strip were examined. One step DSA has been demonstrated effective reduction of Nickel piping by e-beam inspection count, improved NiSi resistance and junction leakage w/o device performance degradation.

Millisecond anneal for ultra-shallow junction applications

As CMOS devices are scaled down, dopant activation, junction profile control and silicide engineering become increasingly important. To address these ultra-shallow junction (USJ) challenges, millisecond anneal (MSA) has emerged as a main stream thermal process technology for advanced CMOS device fabrication. In this paper, we will discuss two major classes of applications for MSA in USJ: achieving effective dopant activation with limited diffusion and to facilitate Ni-based silicidation with reduced leakage. Some issues and process solutions to address them will also be examined.

Conformal SiGe selective epitaxial growth for advanced CMOS technology

For advanced CMOS technology, embedded Silicon Germanium (SiGe) alloys with high Ge% in source/drain is necessary to boost PMOSFET device performance through hole mobility enhancement. Both incoming Si surface quality and SiGe seed layer conformality are critical for the subsequent epitaxial growth of SiGe material with low defect density. In this paper, we reported an in-situ clean method to achieve a pristine Si surface as well as an optimized epitaxial growth process to form conformal SiGe seed layer. With these solutions, a high-quality embedded SiGe source/drain is achieved resulting in 97% reduction in defect density and 7% improvement in PMOS device performance.

Residue defect study on amorphous silicon film

In advanced technology nodes, many new materials have been introduced to improve the device capability. This means new particle sources are also introduced through more complicated process. Hence, the defect control will be more important for manufacturing and yield improvement. In this paper we addressed one type of residue defect found on surface of amorphous silicon film. The defect source and forming mechanism were revealed by our experiments. Finally, the cleaning method was shared that can remove this defect.

Investigation of seal nitride process in 32nm beyond HK/MG technology

Seal nitride process of High-k/Metal Gate (HK/MG) technology is developed from offset nitride process of Poly/SiON technology which is widely used to define the source/drain extension area for overlap capacitor reduction and boron diffusion control of short channel effect improvement. In HK/MG technology era, the seal nitride process becomes more critical than Poly/SiON because the dummy poly will be removed in MG last process. The seal nitride process will not only be used to reduce overlap capacitance, short channel effect improvement, but also the seal nitride height impacts the metal gate electrode height for performance improvement which is retained after lightly doped drain, spacer formation process, etc. In this paper, the comparison between conventional nitride process and in-situ carbon doped seal nitride process is developed to prevent boron diffusion for better short channel effect control, also the process is developed to achieve lower wet etch rate for better critical dimension retention of lightly doped drain implantation control, metal height control after dummy poly removal. A different carbon concentration process is further developed after process tuning with the film characterization of wet etch rate, XPS measurement of impurity components, SIMS for carbon profile check and the electrical data is demonstrated to prove the performance gain.

Post ion implantation photoresist residue removal study

Post ion implantation PR (photoresist) residue removal is a very critical process to obtain higher device yield and enhance circuit reliability. Traditional wet batch cleaning is not recommended for the poor particle performance and pattern damage risk. Instead, Wet SWC (single wafer cleaning) are wildly used. This paper studied the PR residue wet strip process after ions implantation. The SWC can improve the particle performance of the wafers comparing to the batch cleaning. The new chemical was introduced to improve capability of PR residue removal. Finally, the encouraging yield improvement was obtained by the optimized wet SWC process.

Spectrometric ellipsometry application to optical metrology of Silicon-Germanium layer

Now an accurate metrology of Silicon-Germanium (SiGe) thickness and Ge concentration is becoming more and more important for beyond 40nm technology. Traditional solution is normally Transmission Electron Microscope (TEM) for thickness and Second Ion Mass Spectrometry (SIMS) for Ge concentration, which is suffering from sample destruction and makes inline monitoring impossible. On the contrary, optical spectrometric ellipsometry (SE), a non-destructive method with high throughput, can be used to measure SiGe layer thickness and Ge concentration at the same time. In this work, design of experiment (DoE) wafers of multi-layer SiGe stack was used for metrology model setting. The thickness and Ge concentration of each layer were measured. TEM and SIMS work as reference to qualify the model. The metrology stability was also tested if can meet production criteria.

Investigation of embedded silicon germanium typical defect solution for advanced CMOS process

Embedded silicon germanium (e-SiGe) technology in PMOS source/drain area is a trend for advanced CMOS process development. Especially when device gate length reach 28nm or below, sigma shaped trench in PMOS S/D area along with higher germanium and boron concentrations in the SiGe film are needed to improve PMOS channel hole mobility and device Ion/Ioff performance. However, selective epitaxy of SiGe:B will be increasingly challenging as germanium and in-situ boron concentrations increase. The biggest problem is the ball defect showing up after selective epitaxy SiGe processes, which is one of the major killers for device yield. In this paper, we investigated the impact of different wet clean and selective epitaxy conditions on SiGe process defects. For the wet clean experiment, one additional clean step was added to clean the wafer surface after dry etch & wet etch to form the sigma shape trench, followed by chemical to removal of native oxide followed by SiGe: B process. This way we can get best ball defect performance. For selective epitaxy process, seed, bulk & cap layers condition were adjusted. Finally, we found that the cap layer is the most significant factor that could produce SiGe ball defect. By SiGe ball defect reduction, device yield performance has a great improvement.

Laser spike anneal macro & micro non-uniformity investigation using modulated optical reflectance and four-point-probe

Laser spike anneal (LSA) is one of major millisecond anneal techniques for forming ultra-shallow and highly activated junctions. With its ultra-fast heating capability, LSA has found a range of applications in ultra-shallow junction (USJ) applications. However, there are some challenges associated with the technique that need to be effectively addressed to ensure the quality of LSA processes. One of such challenges is macro and micro non-uniformity resulted from LSA process. In this work, the non-uniformity was studied using modulated optical reflectance (MOR) and sheet resistance measurement by four point probe. Significant macro and micro non-uniformity was observed through these metrologies. The impact of LSA process knobs, such as scanning method, overlap percentage and rotation on non-uniformity was investigated.