Jinsub Park

Low power compact design of ARIA block cipher

This paper presents a 32-bit hardware architecture reduced from the original 128-bit ARIA cryptographic algorithm. The hardware design in this paper is a low-power and compact version of ARIA for mobile environment. We use four S-boxes and modify a diffusion function and its data-path to reduce a hardware size. The proposed 32-bit ARIA needs 63 clock cycles to generate initial values for a round key and 356 clock cycles to encrypt a single message packet. The 32-bit ARIA has 13,893 gates. It is 62.5 % smaller than the original 128-bit ARIA. The power consumption is 61.46mW, 9.7% of the 128-bit version at 71MHz

The smallest ARIA module with 16-bit architecture

This paper presented the smallest hardware architecture of the ARIA block cipher algorithm. A 128-bit data block was divided into eight 16-bit blocks to reduce the hardware size. The 16-bit architecture allowed two S-Boxes and 16-bit diffusion operation. We proposed a design for the substitution layer and the memory block. The proposed round key generator processed a 16-bit block of a 128-bit round key for three cycles. The proposed ARIA module with a 128-bit key comprised 6,076 equivalent gates using a 0.18-μm CMOS standard cell library. It took 88 clock cycles to generate four initial values for a round key and 400 clock cycles to en/decrypt 128-bit block data. The power consumption of 16-bit ARIA was only 5.02 μW at 100 kHz 1.8V.

Low Power Cryptographic Design based on Circuit Size Reduction

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip`s 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.