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A Self-Testing Dynamic RAM Chip

A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.

Implementation of VLSI self-testing by regularization

A novel circuit design methodology is developed for comprehensive offline self-testing of nearly regular VLSI circuits. It is based on four major design techniques: circuit partitioning, regularization to produce identical subcircuits (modules), parallel testing of modules, and fault detection by direct comparison of response streams from the modules. A generalization of I-testing called sequential I-testing (SI-testing) is described, which allows identical response streams to be produced at different times and be subsequently synchronized for comparison purposes. The concepts of k-regular and nearly k-regular circuits are introduced, which generalize regular circuits (iterative logic arrays) to array-like circuits that contain several cell-types and are moderately irregular. A heuristic circuit partitioning and regularization method for nearly-regular circuits is described. >

Low power compact design of ARIA block cipher

This paper presents a 32-bit hardware architecture reduced from the original 128-bit ARIA cryptographic algorithm. The hardware design in this paper is a low-power and compact version of ARIA for mobile environment. We use four S-boxes and modify a diffusion function and its data-path to reduce a hardware size. The proposed 32-bit ARIA needs 63 clock cycles to generate initial values for a round key and 356 clock cycles to encrypt a single message packet. The 32-bit ARIA has 13,893 gates. It is 62.5 % smaller than the original 128-bit ARIA. The power consumption is 61.46mW, 9.7% of the 128-bit version at 71MHz

Block Cipher Circuit and Protocol for RFID in UHF Band

This paper proposes a hardware structure and associated finite state machine designs sharing key scheduling circuitry to enhance the performance of the block cypher algorithm, HIGHT. It also introduces an efficient protocol applicable to RFID systems comprising the HIGHT block cipher algorithm. The new HIGHT structure occupies an area size small enough to accommodate tag applications. The structure yields twice higher performance them conventional HIGHT algorithms. The proposed protocol overcomes the security vulnerability of RFID tags and thereby strengthens the security of personal information.

Fault Tolerant Cryptography Circuit for Data Transmission Errors

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

Orientation Tracking Method based on Angular Displacement for Wireless Capsule Endoscope

In this paper, we propose an orientation tracking method and a digestion path model based on angular displacement. The proposed method expresses a capsule`s orientation as 3-dimension vectors and its rotation angle. Errors in roll, pitch, and yaw representing capsule`s orientation information is down to . Using the proposed method we can measure a roll which is not Possible to be measured using the magnetic field method. We reduce algorithm complexity lower than a previous methods based on Euler angle.

Location Determination Scheme based on Proximity Position Data of a Target

This paper describes an improved location determination scheme based on the triangulation method calculating a target position. The proposed scheme uses coordinates of intersection points of three circles each generated by measurement of an observer. The target position obtained from the proposed scheme has higher accuracy not only at the vicinity, but also at the periphery of the observation area. The maximum error and the average error with the proposed scheme are reduced by 40.89% and 40.30%, respectively, with respect to conventional methods.

Fault Tolerant Encryption and Data Compression under Ubiquitous Environment

This paper presents a solution to error avalanche of deciphering where radio noise brings random bit errors in encrypted image data under ubiquitous environment. The image capturing module is to be made comprising data compression and encryption features to reduce data traffic volume and to protect privacy. Block cipher algorithms may experience error avalanche: multiple pixel defects due to single bit error in an encrypted message. The new fault tolerant scheme addresses error avalanche effect exploiting a three-dimensional data shuffling process, which disperses error bits on many frames resulting in sparsely isolated errors. Averaging or majority voting with neighboring pixels can tolerate prominent pixel defects without increase in data volume due to error correction. This scheme has 33% lower data traffic load with respect to the conventional Hamming code based approach.

Low Power Cryptographic Design based on Circuit Size Reduction

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip`s 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.