Seung-Youl Kim

Stromelysin‐3 expression in the differential diagnosis of dermatofibroma and dermatofibrosarcoma protuberans: comparison with factor XIIIa and CD34

Background The distinction between dermatofibroma (DF) and dermatofibrosarcoma protuberans (DFSP) is a well‐known challenge for dermatopathologists. Immunohistochemical stains have been used to augment routine histological examination to aid in differentiating DF from DFSP. Stromelysin‐3 (ST3) is a member of the matrix metalloproteinase (MMP) family, MMP‐11, which is expressed in the skin during wound healing and in the stroma of basal cell carcinoma. Recent studies demonstrated that DFs expressed ST3, whereas DFSPs were only rarely ST3 positive.

Block Cipher Circuit and Protocol for RFID in UHF Band

This paper proposes a hardware structure and associated finite state machine designs sharing key scheduling circuitry to enhance the performance of the block cypher algorithm, HIGHT. It also introduces an efficient protocol applicable to RFID systems comprising the HIGHT block cipher algorithm. The new HIGHT structure occupies an area size small enough to accommodate tag applications. The structure yields twice higher performance them conventional HIGHT algorithms. The proposed protocol overcomes the security vulnerability of RFID tags and thereby strengthens the security of personal information.

Design of CMOS dual antifuse OTP memory based on gate oxide

This paper presents a one-time-programmable ROM based on CMOS dual antifuses achieving high reliability and performance. The CMOS antifuse exploits the gate oxide layer of a typical CMOS process and thereby does not need an additional mask step for antifuse implementation. The proposed antifuse circuit comprises two antifuse nMOS transistors and two pMOS access transistors. Each antifuse cell employs differential architecture. An antifuse cell compares two differential outputs and determines its final output. This dual antifuse cell shows strong reliability against soft-breakdown failure. This high reliability makes the proposed one-time-programmable ROM can be applicable to high reliability such as encryption systems.

Location Determination Scheme based on Proximity Position Data of a Target

This paper describes an improved location determination scheme based on the triangulation method calculating a target position. The proposed scheme uses coordinates of intersection points of three circles each generated by measurement of an observer. The target position obtained from the proposed scheme has higher accuracy not only at the vicinity, but also at the periphery of the observation area. The maximum error and the average error with the proposed scheme are reduced by 40.89% and 40.30%, respectively, with respect to conventional methods.

Fault Tolerant Encryption and Data Compression under Ubiquitous Environment

This paper presents a solution to error avalanche of deciphering where radio noise brings random bit errors in encrypted image data under ubiquitous environment. The image capturing module is to be made comprising data compression and encryption features to reduce data traffic volume and to protect privacy. Block cipher algorithms may experience error avalanche: multiple pixel defects due to single bit error in an encrypted message. The new fault tolerant scheme addresses error avalanche effect exploiting a three-dimensional data shuffling process, which disperses error bits on many frames resulting in sparsely isolated errors. Averaging or majority voting with neighboring pixels can tolerate prominent pixel defects without increase in data volume due to error correction. This scheme has 33% lower data traffic load with respect to the conventional Hamming code based approach.

Low Power Cryptographic Design based on Circuit Size Reduction

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip`s 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.