Jizhi Liu

A New High Holding Voltage Dual-Direction SCR With Optimized Segmented Topology

While silicon controlled rectifiers (SCRs) are highly robust electrostatic discharge (ESD) protection devices, they typically are not suited for high-voltage ESD protection due to their inherently low holding voltage and thus vulnerability to latch-up threat. In this letter, a new high holding voltage dual-direction SCR (NHHVDDSCR) with a small area and optimized topology is developed in a 0.18-μm CMOS technology. The results of the NHHVDDSCR and other SCR devices measured from the transmission line pulsing are compared and discussed. It is shown that the NHHVDDSCR can possess a relatively high and adjustable holding voltage, as well as an acceptable failure current for robust ESD protection of high voltage applications.

Segmented SCR for high voltage ESD protection

Typical SCR with stripe layout style is modified into segmented one in order to tune the SCRs holding voltage for the ESD protection in different operation voltage domain. SCRs with different segmented style and ratio were made, and according to TLP test results, the most proper one for high voltage ESD protection is selected among them. By delicate layout design and choosing the right segmentation pattern and ratio, the holding voltage of the SCR is obviously lifted to a high level of over 30 V, a high enough value to obtain latch-up immunity.

The segmented SCRs with optimized holding voltage for on-chip ESD protection

Segmentation technique for optimizing the holding voltage of SCR is discussed and implemented in a 0.6μm SOI process. Based on the prior researches, the holding voltage of SCR is a key parameter for latch-up risk assessment. The segmented SCR with external resistor paralleled with the parasitic Ptub resistor is proposed by modifying the layout, and the holding voltage can be increased. The TLP characterization results show that the holding voltage is affected by the ratio, width of the segmentations and the resistance of the external resistor. The factors related to the holding voltage can be traded off for specific applications. Meanwhile, the equivalent schematics and mechanism of the proposed structures are also investigated briefly in this paper.

Low Trigger Voltage and High Turn-On Speed SCR for ESD Protection in Nanometer Technology

As CMOS technology scales down to the nanometer technology, the thickness of the gate oxide becomes thinner and thinner, the breakdown voltage of the gate oxide reduces largely. It is imperative to reduce the trigger voltage and improve the turn-on speed of the SCR for ESD protection. In order to reduce the trigger voltage, a novel gate-coupled silicon-controlled rectifier (GCSCR) device is proposed without using an external trigger circuit. In the GCSCR structure, there is a parasitic RC sub-network which can provide a potential to make the SCR turn on. The trigger voltage of the GCSCR is lower than that of the conventional SCR device to effectively protect the interior CMOS circuits. The simulation and experimental results show that the trigger voltage of the GCSCR can be adjusted by changing the sizes of the device layout parameters and the ESD robustness of the GCSCR is same as the conventional LVTSCR. For improving the turn-on speed of the SCR, a new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed for electrostatic discharge (ESD) protection. Through theoretical analysis, the turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR. The VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the SCR with the VLBD structure (VSCR) is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.

A novel GCSCR structure for ESD protection application

A novel gate-coupled silicon-controlled rectifier (GCSCR) device is proposed and realized in a 0.35-um BiCMOS process for electrostatic-discharge (ESD) applications. Without using an external trigger circuitry, the GCSCR has a trigger voltage as low as 9 V to effectively protect deep-submicrometer MOS circuits. The ESD robustness of the novel SCR in positive operations are higher than 60mA/um, thus the new device is more suitable for low-voltage integrated circuit ESD protection applications.

New fast turn-on speed SCR device for electrostatic discharge protection

Abstract A new SCR with the variation lateral base doping (VLBD) structure (VSCR) is proposed to improve the turn-on speed for electrostatic discharge (ESD) protection. The turn-on speed of the SCR was determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors of the SCR, and the VLBD structure can reduce the base transit time of the bipolar transistors to improve the turn-on speed of the SCR. The experimental and simulation results show that the turn-on time of the VSCRs with the VLBD structure is 12% less than that of the MLSCR with the traditional uniform base doping without adding extra process masks and increasing the chip area.

A reliability-boosted ferroelectric random access memory with random-dynamic reference cells

Generating reference signal is indispensable and challenging in ferroelectric random access memory using one-transistor and one-capacitor architecture. This work presents an architecture with random-dynamic reference scheme for high speed and high reliability application. The detailed scheme and operating principle are illustrated. By rewriting memory cells and reference cells simultaneously after read process, the cycle time can be reduced. The data rewritten into reference cells are related to the data in memory cells, which can realize rewriting randomly “0” or “1” into reference cells. This method can balance the switch times of the pair of reference capacitors and restrain the floating of reference voltage generated for data read process, resulting in boosted reliability in the proposed architecture. A prototype based on the proposed architecture is fabricated and verified. It is exhibited that the proposed method can effectively reduce the cycle time and improve the operating speed.

High-speed and low-power FRAM with a bitline-segmental array

A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 μ m 3-metal process and functionally verified.