Joachim Kunkel

Hardware synthesis from C/C++

Before attempting to synthesize hardware from a programming language like C or C++, we need to introduce additional semantics to be able to describe hardware behavior accurately. In particular, concurrency, reactivity, communication mechanisms, and event handling semantics need to be added, Also, a synthesizable subset of the language needs to be defined, together with synthesis semantics for programming language constructs. With these enhancements, it is possible to create C/C++ descriptions of hardware at the well-understood RTL and behavioral levels of abstraction, providing an opportunity to leverage existing, mature hardware-synthesis technology that has been developed in the context of HDL based synthesis to create a C/C++ synthesis system. In this paper, we will present some of the key ingredients of a C/C++ synthesis system and elaborate on the challenges of hardware synthesis from C/C++.

System level design using C

This paper discusses the use of C++ for the design of digital systems. The paper distinguishes a number of different approaches towards the use of programming languages for digital system design and will discuss in more detail how C++ can be used for system modeling and refinement, for simulation, and for architecture design.

Embedde computing - Toward IP-based system-level soc design

SystemC v2.0 delivers a robust system-level design language that describes both hardware and software from concept through implementation.

Transaction Based Design: Another Buzzword or the Solution to a Design Problem?

Complex systems on chip (SoCs) present challenges in the design and verification process that cannot be adequately addressed by traditional methodologies based on register transfer descriptions. Some of the aspects are efficient design exploration based on component reuse, getting closure on the architecture, as well as early development, integration and verification of embedded software. In search for responses to these challenges, Transaction level modeling (TLM) has got quite some attention in the area of SoC design. This panel attempts to do a reality check on TLM from an engineering point of view. Questions to discuss are: Is the Transaction Level (TL) really useful for the design and/or for the verification of SoCs? How can TL speed up the design process and lowering the risk of design failures? What are the implications on tools, languages, and Intellectual Property (IP) used in the design/verification process? The panelists will share their thoughts on transaction based design and verification, and will discuss benefits and issues based on their experiences of applying transaction level methodologies.

Panel Discussion: Life Begins at 65 - Unless You Are Mixed Signal?

The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? Which solutions that help in increasing design efficiency are currently on the table? In the future, which side of the table will analog designers of Bob Peases generation sit: the IP provider or the chip company? Or are their skills redundant for the 65 nm analog design challenges?

The future of system design languages (panel session)

Verilog HDL was a breakthrough for the hardware design community in 1986. Over the years, the methodology based on the Verilog HDL has been extended with utilities and enhancements. With 0.25- and 0.18 µ processes enabling a system to be packed onto a single integrated circuit (IC), design problems have surfaced that no one could have predicted 13 years ago. As a result, several new design language proposals have been introduced since the last Design Automation Conference (DAC), all claiming to aid system-on-chip (SOC) design. Several claim to improve the designers ability to efficiently create, implement, and verify SOC designs from architectural specification through functional implementation. The panel, comprised of experienced designers and representatives of organizations submitting design language proposals, will debate the various proposals and will try to identify what future trend will accelerate system design. Questions and issues to be considered include:Whats in store for the future — C, Java, Superlog, HDL or SLDL? A comparison of modeling, gate-level and behavioral simulation capabilities of a new design language to current languages/tools/methods A comparison of the software development capabilities of a new design language to current languages/tools/methods A review of the projected design environment of a new design language to current languages/tools/methods.

Are we there yet? Has IP block assembly become as easy as LEGO?

With the majority of chip real estate being filled with re-used IP blocks, the process of block assembly has significantly grown in importance. Marketing literature seems to suggest that assembling a chip from IP is as easy as browsing a library of blocks, assembling them in a block diagram and then pushing a button.