Joao Antonio Martino
Centro Universitário da FEI
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Featured researches published by Joao Antonio Martino.
international caribbean conference on devices, circuits and systems | 2006
Marcelo Antonio Pavanello; A. Cerdeira; Joao Antonio Martino; Jean-Pierre Raskin; Denis Flandre
In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and gate-all-around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion
Proceedings of the 215th ECS Meeting | 2009
Joao Antonio Martino; Michele Rodrigues; Abdelkarim Mercha; Eddy Simoen; Cor Claeys
The aim of this work is to study for the first time the gate induced floating body effect (GIFBE) of triple gate nFinFETs devices with different gate stack options for working function (WF) engineering. Based on electrical characterizations it is shown that the presence of a cap layer like Dy2O3 increases EOT and reduces the gate effective WF which decrease VFB and VT. As a consequence the transconductance also decreases and a positive shift of the onset of the GIFBE is observed both at room and at high temperature.
Meeting Abstracts | 2007
Marcelo Antonio Pavanello; Joao Antonio Martino; Eddy Simoen; Rita Rooyackers; Nadine Collaert; Cor Claeys
This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-K dielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures. In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement.
international soi conference | 2006
Marcelo Antonio Pavanello; Joao Antonio Martino; Eddy Simoen; Rita Rooyackers; Nadine Collaert; C. Claeys
This paper presents, for the first time, the operation of triple-gate FinFETs with HfO<sub>2</sub> gate dielectric, TiN gate and undoped body at cryogenic temperatures. Emphasis for the most common analog figures of merit is given as the intrinsic gain (A<sub>V</sub>) and the unity gain frequency (f<sub>T</sub>)
Meeting Abstracts | 2013
Caio Cesar Mendes Bordallo; Paula Ghedini Der Agopian; Joao Antonio Martino; Eddy Simoen; C. Claeys
The multiple-gate devices (MuGFET) show a better scalability than single gate ones due to their better short channel effects and higher radiation hardness (1). However, the vertical structure presents a smaller effective electron mobility due to the lateral conduction on the (110) plane. In order to improve the carrier’s mobility different stress techniques have been used (2). In this work, the impact of proton irradiation on devices with a high stress effect (biaxial+uniaxial stress on the same device) is evaluated for triple-gate SOI nMOSFETs at room and high temperature. All studied devices were fabricated in imec, Belgium. They have the following characteristics: fin height of 65 nm and fin width (WFIN) ranging between 20 and 870 nm, channel length of 150 nm and buried oxide of 150 nm. The gate dielectric consists of 2 nm HfSiON on 1 nm SiO2. The gate electrode is composed by 10 nm of TiN under 100 nm of polysilicon. In order to reduce the series resistance, all devices have source/drain (S/D) contacts with Selective Epitaxial Growth (SEG). Further process details can be found in (3). The 60 MeV proton irradiations have been performed at the Cyclone facility in Louvain-la-Neuve (Belgium) up to a fluence of 10 p/cm. The tensile stress and proton irradiation influence on the transconductance (gm) behavior at room temperature is analyzed from fig.1. The additive effect of uniaxial+biaxial tensile stress is responsible for the large gm increase due to the electron mobility enhancement and for the considerable threshold voltage (Vth) reduction caused by the band gap narrowing. Emphasizing the proton irradiation influence on the nMuGFET behavior, only for WFIN≥120 nm it was possible to observe a small reduction in maximum transconductance (gmmax). The radiation influence on Vth is mainly due to the oxide and interface trap charges at the back interface since the front gate dielectric is very thin and consequently the radiation influence on it is negligible. Figure 2 shows that both the tensile stress and the proton irradiation promote an IGIDL degradation (higher IGIDL). Since the tensile stress causes a reduction of the band gap, due to the conduction ( Ec) and valence ( Ev) band-offsets (4), a higher Gate Induced Drain Leakage (GIDL), that is band-to-band tunneling in the gate to drain overlap region (5), is observed. The additive effect of the tensile stress (biaxial+uniaxial) causes a strong band gap narrowing and a strong GIDL increase. On the other hand, the proton irradiation causes both buried oxide charges and a change in the oxide trapped charge density. While the first one is responsible for the threshold voltage reduction at the back interface and consequently for the back leakage current increase, the last one enhances BTBT (6) increasing GIDL. As a result, the radiation also promotes a strong IGIDL degradation. For all analyses, the temperature increase results in a higher IGIDL degradation. Analyzing the fin width (WFIN) impact on IGIDL (fig. 3), considering only the unstressed devices, the direct relationship between leakage current and WFIN is clear. Besides, as the fin width increases, the buried oxide is more exposed to radiation effects and consequently a higher IGIDL is observed. The temperature increase also contributes to a GIDL increase due to the band gap narrowing, increasing even more the off-state current. Since narrow fin devices present a small IGIDL and a small radiation effect, the wider fin was taking into consideration in order to make a comparison between the splits. Taking the unstrained device as a reference, from figure 4 it is possible to compare the influence of each effect (proton irradiation and biaxial+uniaxial stress) on off-current. From figure 4A it is possible to see that the additive effect of the mechanical stress (biaxial+uniaxial) is more harmful than the proton radiation. At the same time, when wide strained devices are submitted to the radiation, the off-current reaches unacceptable values (4.4 A at room temperature), resulting in a very low ION/IOFF ratio. From figure 4B it is possible to notice that the IGIDL increases almost one order of magnitude when temperature increases from 20oC to 100oC, for both strained and unstrained devices. Since the IGIDL showed to be more sensitive to the temperature than the ION , the ION/IOFF ratio can be even worse at high temperatures.
international soi conference | 2005
Marcelo Antonio Pavanello; Joao Antonio Martino; Eddy Simoen; C. Claeys
This work demonstrated that the saturation threshold voltage of short-channel SOI nMOSFETs degrades as the temperature is reduced. The V/sub T/ degradation at low temperatures is caused by a combination between the floating-body and impact ionization effects, increasing the gain of the parasitic bipolar structure. The halo or pocket implantation contributes for the enhanced V/sub T/ degradation at lower temperatures. The absence of halo efficiently reduces both the V/sub T/ variation and the V/sub T/ degradation in cryogenic operation. A negative biasing of the back gate tends to enhance the V/sub T/ degradation with temperature.
Solid-state Electronics | 2007
Marcelo Antonio Pavanello; Joao Antonio Martino; Eddy Simoen; Rita Rooyackers; Nadine Collaert; Corneel Claeys
ECS Transactions | 2013
Joao Antonio Martino; Victor Sonnenberg; M Galeti; Marc Aoulaiche; Eddy Simoen; C. Claeys
Journal of Integrated Circuits and Systems | 2010
Sara dos Santos; Joao Antonio Martino; Eddy Simoen; Cor Claeys; Luciano Gualberto
227th ECS Meeting (May 24-28, 2015) | 2015
Vitor T. Itocazu; Katia R. A. Sasaki; Matheus Barros Manini; Victor Sonnenberg; Joao Antonio Martino; Eddy Simoen; Cor Claeys