Paula Ghedini Der Agopian

Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature

This paper presents, for the first time, the experimental comparison between the p-type trigate FinFET and trigate p-TFET analog performances for devices fabricated on the same wafer. A careful analysis of the electrical characteristics is performed to choose the best bias conditions for the analog comparison between these devices. A higher intrinsic voltage gain is obtained for p-TFET devices because of their better output conductance, which is more than four orders of magnitude better than the one obtained for p-FinFET transistors at the same bias conditions from room temperature up to 150 °C.

Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs

The goal of this paper is to study the analog performance parameters of tunnel field-effect transistors (TFETs) with different source compositions and process conditions. The experimental matrix included devices with either a 100% silicon or Si1-xGex source, so that the germanium amount at the source/channel interface could be correlated with the prevailing transport mechanism and its impact on transconductance (gm), output conductance (gDS), and early voltage (VEA) could be analyzed. The used process conditions were highlighted by comparing a reference split with no Si passivation to the cases with 12 and 18 Si monolayers to determine their influence on the interface trap density and eventual reduction of the traps in the gate oxide. All these process parameters enable to make conclusions on the intrinsic voltage gain (AV) and the low-frequency noise. Based on these results, the suitability of each type of TFET has been discussed, revealing that 100% Si may still be considered

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2–0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.

NW-TFET analog performance for different Ge source compositions

The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain (AV) due to their better output conductance (less drain electric field penetration than for 46%). The Si source NW-TFET presented the worst analog behavior at lower gate bias. However, when VGS increases, smaller is its AV degradation making it equal or better than the value obtained for SiGe source devices, since in the former the Trap Assisted Tunneling (TAT) is predominant. The peculiar NW-TFET low frequency noise behavior is also presented.

Influence of 60-MeV Proton-Irradiation on Standard and Strained n- and p-Channel MuGFETs

In this work the proton irradiation influence on Multiple Gate MOSFETs (MuGFETs) performance is investigated. This analysis was performed through basic and analog parameters considering four different splits (unstrained, uniaxial, biaxial, uniaxial+biaxial). Although the influence of radiation is more pronounced for p-channel devices, in pMuGFETs devices, the radiation promotes a higher immunity to the back interface conduction resulting in the analog performance improvement. On the other hand, the proton irradiation results in a degradation of the post-irradiated n-channel transistors behavior. The unit gain frequency showed to be strongly dependent on stress efficiency and the radiation results in an increase of the unit gain frequency for splits with high stress effectiveness for both cases p- and nMuGFETs.

Fin shape influence on the analog performance of standard and strained MuGFETs

From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner Wmid there is a performance increase of up to 3 dB on intrinsic voltage gain compared to rectangular shape. Strained devices present better AV and fT, both following the gm tendency for each channel length.

Impact of the diameter of vertical nanowire-tunnel FETs with Si and SiGe source composition on analog parameters

In this work, the impact of the diameter on vertical nanowire Tunnel FETs analog parameters is evaluated experimentally and by numerical simulation, comparing two different source compositions, one with Si and another with Si73Ge27. The SiGe source device presents a higher tunneling current when compared with the Si source device, resulting in an increase of both transconductance (gm) and output conductance (gD). For a diameter (Def) higher than 70nm, the reduction of Def decreases both gm and gD due to the decrease of the conducting area. In order to extrapolate the results for smaller diameters, some numerical simulations were performed and show that the predominant transport mechanism for 30 nm diameter is band-to-band tunneling (BTBT), which are more drain voltage dependent. As a result, a strong degradation of gD and intrinsic voltage gain (Av) was observed due to the increase of the generation rate by the enhanced tunneling.

Comparison between vertical silicon NW-TFET and NW-MOSFETfrom analog point of view

In this work a comparison of the analog performance between vertical silicon Nanowires Tunnel Field Effect Transistors (NW-TFETs) and nanowires MOSFETs (NW-MOSFETs) is performed mainly focusing on the basic analog characteristics at room and high temperatures for the first time. The opposite transconductance trend as a function of temperature and the much lower (better) output conductance obtained for NW-TFETs when compared to NW-MOSFETs contribute to an important improvement of the intrinsic voltage gain, making the NW-TFETs a good alternative for analog applications.

Study of the linear kink effect in PD SOI nMOSFETs

We present in this work a study of the linear kink effect (LKE) occurrence in partially depleted (PD) SOI nMOSFETs with thin gate oxide. The experimental LKE dependence on the channel length, channel width and drain voltage are reported as well as the impact of various parameters on the second peak has been studied by two-dimensional numerical simulations, namely, the gate current level, the carrier lifetime, the increase of the body potential, the threshold voltage variation and AC analysis. Three-dimensional simulations were also performed in order to evaluate the LKE dependence on the channel width.

Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures

In this work the intrinsic voltage gain (AV) is for the first time experimentally analyzed for a planar Line-TFETs and its performance is compared with different MOSFET and point TFET architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. The Line-TFET shows a much better intrinsic voltage gain than all studied MOSFET devices (FinFET and GAA). However, when it is compared to other TFET structures, Line-TFETs show a worse AV. Besides the AV, a higher on-state current was obtained for Line-TFETs, which leads to a good compromise for analog application.