Marcelo Antonio Pavanello

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Threshold voltage in junctionless nanowire transistors

This work presents a physically based analytical model for the threshold voltage in junctionless nanowire transistors (JNTs). The model is based on the solution of the two-dimensional Poisson equation and includes the dependence on JNT width, height and doping concentration. The quantum confinement has also been taken into consideration in the model formulation. The model is validated using experimental results of nMOS and pMOS JNTs, and three-dimensional TCAD simulations where the nanowire width and height, doping concentration, gate oxide thickness and temperature have been varied. The gate oxide capacitance is also addressed aiming to adequately calculate the capacitance in non-planar devices. The temperature influence on the threshold voltage of JNTs is also analyzed. The presented model shows excellent agreement with both experimental and simulated data, adequately describing the JNT threshold voltage.

Analog performance and application of graded-channel fully depleted SOI MOSFETs

The performances of the single-transistor operational transconductance amplifiers (OTAs) implemented using graded-channel (GC) and a conventional fully depleted silicon-on-insulator nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs

Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects

An extended study of the occurrence of inherent parasitic bipolar effects in conventional and graded-channel fully depleted silicon-on-insulator nMOSFETs is carried out. The graded-channel device is a new asymmetric channel MOSFET, fabricated through a simple process variation. Measurements and two-dimensional simulations are used to demonstrate that the graded-channel device efficiently alleviates the parasitic BJT action, improving the breakdown voltage, by the reduction of impact ionization in the high electric field region. Based on process/device simulation and modeling, multiplication factor and parasitic bipolar gain, which are the responsible parameters for the parasitic BJT action, are investigated separately providing a physical explanation. The abnormal subthreshold slope and hysteresis phenomenon are also studied and compared

Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model.

An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics

A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasitic bipolar effects in fully depleted silicon-on-insulator (SOI) devices and improving the output characteristics is introduced. Measurements and two-dimensional simulations are used to study the device capabilities and limitations

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.

Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor

In this paper, we analyze the previously unexpected advantages of asymmetric channel engineering on the MOS resistance behavior in quasi-linear operation, such as used in integrated continuous-time tunable filters. The study of the two major figures of merit in such applications as on-resistance and nonlinear harmonic distortion, is supported by both measurements and simulations of conventional and graded-channel (GC) fully depleted silicon-on-insulator (SOI) MOSFETs. The quasi-linear current-voltage characteristics of GC transistors show a decrease of the on-resistance as the length of the low doped region in the channel is increased, as well as an improvement in the third-order harmonic distortion (HD3), when compared with conventional transistors. A method for full comparison between conventional and GC SOI MOSFETs is presented, considering HD3 evolution with on-resistance tuning under low voltage of operation. Results demonstrate the significant advantages provided by the asymmetrical long channel transistors.

Analog circuit design using graded-channel silicon-on-insulator nMOSFETs

An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (1713) transistors is performed. Performances of single-transistor operational transconductance amplifier (OTA) implemented using GC and conventional FD SOI nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs. Two-dimensional simulations are used to analyze the intrinsic-gate capacitances in linear and saturation regions, establishing that GC transistors present almost the same capacitive amount than the conventional FD transistors in a typical analog range of operation. Current mirrors fabricated using GC and conventional MOSFETs are compared. It is demonstrated that GC MOSFETs can provide high precision current mirrors with enhanced output swing

An explicit multi-exponential model for semiconductor junctions with series and shunt resistances

An alternative explicit multi-exponential model is proposed to describe multiple, arbitrary ideality factor, conduction mechanisms in semiconductor junctions with parasitic series and shunt resistances. This Lambert function based model allows the terminal current to be expressed as an explicit analytical function of the applied terminal voltage, in contrast to the implicit-type conventional multi-exponential model. As a result this model inherently offers a higher computational efficiency than conventional models, making it better suited for repetitive simulation and parameter extraction applications. Its explicit nature also allows direct analytic differentiation and integration. The model’s applicability has been assessed by parameter extraction and subsequent playback using synthetic and experimental diode forward I–V characteristics.