Jochen Kuhmann

Oxidation and reduction kinetics of eutectic SnPb, InSn and AuSn: a knowledge base for fluxless solder bonding applications

For microelectronics and especially for upcoming new packaging technologies in micromechanics and photonics fluxless, reliable and economic soldering technologies are needed. In this article, we consequently focus on the oxidation and reduction kinetics of three commonly used eutectic solder alloys: (1) SnPb; (2) InSn; (3) AuSn. The studies of the oxidation kinetics show that the growth of the native oxide, which covers the solder surfaces from the start of all soldering operations is self-limiting. The rate of oxidation on the molten, metallic solder surfaces is significantly reduced with decreasing O/sub 2/ partial-pressure. Using in situ Auger electron spectroscopy (AES) it could be shown for the first time, that H/sub 2/ can reduce Sn-oxide as well as In-oxide at moderate heating duration and temperatures. In the second part of this study, the results, obtained by the investigation of oxidation and reduction kinetics, are applied to flip-chip (FC) bonding experiments in vacuum with and without the injection of H/sub 2/. Wetting in vacuum is excellent but the self-alignment during flip-chip soldering is restricted. The desired, perfectly self-aligned FC-bonds have been only achieved, using evaporated and reflowed AuSn(80/20) and SnPb(60/40) after the introduction of H/sub 2/.

Chip-size-packaged silicon microphones

The first results of silicon microphones that are completely batch-packaged and integrated with signal conditioning circuitry in a chip stack are discussed. The chip stack is designed to be directly mounted into a system, such as a hearing instrument, without further single-chip handling or wire bonding. The devices are fully encapsulated and provided with a well-determined interface to the environment. The integrated microphones operate at a bias of 1.5 V and are expected to reach a sensitivity of 5 mV/Pa, an A-weighted equivalent input noise of 24 dB sound pressure level, and a power consumption of about 50 μW in the near future, thereby living up to the tight specifications of microphones for hearing instruments. Other potential applications include mobile phones, headsets, and wearable computers, in which space is constrained.

Ultra thin hermetic wafer level, chip scale package

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing

Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) HermeticThrough-Wafer Connections in Silicon

We present the design, fabrication technology, and experimental evaluation of the high frequency performance of a new type of hermetically sealed through-wafer interconnects (mu-vias) in silicon substrates. The application of these mu-vias for wafer-scale hermetic packaging of receiver and transmitter optical subassemblies at 10Gbit/s, and for packaging of micro electro mechanical devices (MEMS) is discussed. These examples illustrate the potential of the technology to simplify the design of e.g. ball grid array packages (BGAs) in a cost effective way without sacrificing RF performance even at very high frequencies. Bandwidth measurements of the mu-via structures show reflections below -25dB up to 35GHz in a coplanar configuration even with multiple mu-vias in the path of a 50 Omega coplanar line. Additional losses due to the mu-vias are very low and below the detection limit of a 2.5mm long path. The waveguide losses were about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz. Excellent performance of the mu-vias is achieved by reducing their effective depth. On a 350mum or 500mum thick substrate the effective via depth can e.g. be reduced to only 20mum. The remaining depth is covered by impedance controlled coplanar lines that run down the slanted side wall of cavities in the silicon substrate. The concept thus combines the mechanical stability of substrates that are a few hundreds of microns thick with the ease to fabricate mu-vias in a membrane that is only a few tenths of microns thick. The pitch of these vias can be below 100 mum allowing for very high density interconnects as e.g. required in packaging of multi channel optical modules. The coplanar lines on the cavity side walls are realized by 3D photolithography using an electro-deposited photoresist and proximity exposure. The cavities with angled side walls are wet etched in aqueous KOH solution from one side of the substrate leaving a thin membrane in the bottom of the cavity (e.g. 20mum). This membrane is then opened up from the back side at the locations of the mu-vias in an additional KOH etching step. After structuring the metal lines the openings in the membranes are hermetically sealed by metal plating. The metallization scheme on which the vias and the electrical leads are based is compatible with reflow soldering and wire bonding. As an additional advantage the cavities can be enlarged and used as head room for discrete electro/optical components that are assembled on a lid wafer, or the components can be directly assembled in the cavity. Coplanar metal lines in combination with the proposed via technology allow the impedance matched connection of these high speed components to a ball grid array (BGA) on the back side of the hermetic enclosure which in turn can be soldered to a rigid circuit board or to a flexible circuit board. Due to the tight control of tolerances and the dense via pitch it is easily possible to route multiple RF ports in and out of the package even in differential configurations and with additional DC control signals while still maintaining a very small footprint and excellent signal integrity. The presented via technology is not only able to fulfill todays requirements in hermetic and cost effective packaging of high bit rate electro/optical modules but scales to bit rates above 40GHz and to packages with very large numbers of I/O counts

A silicon wafer packaging solution for HB-LEDs

In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

Fluxless FC-soldering in O/sub 2/ purged ambient

This paper describes a straightforward approach to fluxless flip-chip soldering: bonding in ambient with reduced O/sub 2/ partial pressure. Using as-deposited SnAg solder bumps and in-situ reflow, impressively strong self-alignment could be achieved, which resulted in a complete overlap of chip metallization and solder bumps. The results of this work have been successfully transferred to reflow furnaces with N/sub 2/ and N/sub 2//H/sub 2/ purge, suitable for batch processing.

Processing and performance of broadband integrated resistor structures on non-planar topologies in hermetic silicon enclosure with vertical micro vias

We present the integration of thin film nickel-chromium (NiCr) resistors into a hermetic, 3D structured silicon packaging platform for wafer level sealing and demonstrate their performance as broadband passive components. Resistors on the cavity side walls can be designed by modeling the material deposition as a unidirectional flux