Ralf Hauffe

Ultra thin hermetic wafer level, chip scale package

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing

Optimized Micro-Via Technology for High Density and High Frequency (>40GHz) HermeticThrough-Wafer Connections in Silicon

We present the design, fabrication technology, and experimental evaluation of the high frequency performance of a new type of hermetically sealed through-wafer interconnects (mu-vias) in silicon substrates. The application of these mu-vias for wafer-scale hermetic packaging of receiver and transmitter optical subassemblies at 10Gbit/s, and for packaging of micro electro mechanical devices (MEMS) is discussed. These examples illustrate the potential of the technology to simplify the design of e.g. ball grid array packages (BGAs) in a cost effective way without sacrificing RF performance even at very high frequencies. Bandwidth measurements of the mu-via structures show reflections below -25dB up to 35GHz in a coplanar configuration even with multiple mu-vias in the path of a 50 Omega coplanar line. Additional losses due to the mu-vias are very low and below the detection limit of a 2.5mm long path. The waveguide losses were about 0.13dB/mm at 10GHz and about 0.28dB/mm at 40GHz. Excellent performance of the mu-vias is achieved by reducing their effective depth. On a 350mum or 500mum thick substrate the effective via depth can e.g. be reduced to only 20mum. The remaining depth is covered by impedance controlled coplanar lines that run down the slanted side wall of cavities in the silicon substrate. The concept thus combines the mechanical stability of substrates that are a few hundreds of microns thick with the ease to fabricate mu-vias in a membrane that is only a few tenths of microns thick. The pitch of these vias can be below 100 mum allowing for very high density interconnects as e.g. required in packaging of multi channel optical modules. The coplanar lines on the cavity side walls are realized by 3D photolithography using an electro-deposited photoresist and proximity exposure. The cavities with angled side walls are wet etched in aqueous KOH solution from one side of the substrate leaving a thin membrane in the bottom of the cavity (e.g. 20mum). This membrane is then opened up from the back side at the locations of the mu-vias in an additional KOH etching step. After structuring the metal lines the openings in the membranes are hermetically sealed by metal plating. The metallization scheme on which the vias and the electrical leads are based is compatible with reflow soldering and wire bonding. As an additional advantage the cavities can be enlarged and used as head room for discrete electro/optical components that are assembled on a lid wafer, or the components can be directly assembled in the cavity. Coplanar metal lines in combination with the proposed via technology allow the impedance matched connection of these high speed components to a ball grid array (BGA) on the back side of the hermetic enclosure which in turn can be soldered to a rigid circuit board or to a flexible circuit board. Due to the tight control of tolerances and the dense via pitch it is easily possible to route multiple RF ports in and out of the package even in differential configurations and with additional DC control signals while still maintaining a very small footprint and excellent signal integrity. The presented via technology is not only able to fulfill todays requirements in hermetic and cost effective packaging of high bit rate electro/optical modules but scales to bit rates above 40GHz and to packages with very large numbers of I/O counts

Silicon micro machined hermetic packaging technology for optical subassemblies

A novel technology for building hermetic optical subassemblies based on silicon is presented which supports precision alignment features, integration of passives, outstanding RF-performance and waferscale assembly and testing. Examples of OSAs will be shown

Application and RF performance of integrated resistor structures on non-planar topologies in micro-machined silicon packages for transmitter optical subassemblies

A hermetic active optical component package is presented which incorporates a resistive metallization layer on the component submount, which allows structuring resistors of a large range of resistances. The use of such integrated resistors for impedance matching applications and in broadband RF chokes are discussed. Designs, simulations and measurements are presented, which demonstrate the reduction in footprint possible by integrating the matching resistor on sloped side-walls, and how an appropriately designed RF choke inside the package can enable advanced testing procedures such as wafer-scale laser diode burn-in with simultaneous RF performance characterization

Beam steering system using a 2D MEMS scanner

Fiber optical modules manufacturing have been recognized as a key challenge in meeting the anticipated demand for high bandwidth telecommunication equipment. Among all challenges, submicron optical alignment for single mode fiber remains the predominant difficulty [1]. To reduce the alignment effort during the assembly, a XY micro stage has been developed. It consists of a scanning platform with a mounted micro-lens on top (Figure 1). After a passive alignment of the components and the sealing of the package, a fine tuning of the lens position and thus the optical coupling efficiency can be made by actuating the MEMS chip.

Processing and performance of broadband integrated resistor structures on non-planar topologies in hermetic silicon enclosure with vertical micro vias

We present the integration of thin film nickel-chromium (NiCr) resistors into a hermetic, 3D structured silicon packaging platform for wafer level sealing and demonstrate their performance as broadband passive components. Resistors on the cavity side walls can be designed by modeling the material deposition as a unidirectional flux