Jochen Verbrugghe

A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time

Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conventional AC-coupled BM- RX has an inherent tradeoff between short settling time and decision threshold droop, which makes an RX settling time shorter than 400ns hard to achieve. Some techniques have been developed to overcome this limitation, demonstrating a settling time of 150 to 200ns. Our previous work uses feed-forward automatic offset compensation (AOC) to achieve a response time as short as 25.6ns. However, a feed-forward scheme using peak detectors is intrinsically less accurate and results in relatively high power consumption. In this paper, we present a DC-coupled 10Gb/s BM-TIA and burst-mode limiting amplifier (BM- LA) chipset that uses a feedback type AOC circuit with switchable loop BW. This new technique is capable of removing input DC offset in less than 75ns, and offers continuous decision threshold tracking during payload, to cope with the maximum length of CID. The differential TIA output port senses a CM reset signal provided by the succeeding BM-LA, and activates an on-chip reset and lock function. This BM-LA also integrates auto reset/activity generation circuits providing the AOC BW switching signal, so that this time-critical signal is not required from the PON system.

Experiments on a 10 Gb/s fast-settling high-sensitivity burst-mode receiver with on-chip auto-reset for 10G-GPONs [Invited]

This paper presents a 10 Gb/s avalanche-photodiode-based DC-coupled reshaping and reamplifying (2R) burst-mode receiver with on-chip auto-reset generation and multiple data rate support, designed for 10G-GPONs. A short 2R settling time of 75 ns (150 ns for lower-rate operation), a high receiver sensitivity of -31.3 dBm, and a large loud/soft ratio of 25.3 dB are demonstrated at 2.5/5/10 Gb/s in burst-mode operation. Allowing multi-rate operation without external reset signals, it shows great potential for use in emerging symmetric 10G-GPON systems and allows for more flexible future optical access networks.

A 40-Gb/s Transimpedance Amplifier for Optical Links

This letter presents a low-power transimpedance amplifier (TIA), supporting both 25 and 40-Gb/s communication. It exhibits an optical modulation amplitude sensitivity of -10.6 dBm at 25 Gb/s and -6.4 dBm at 40 Gb/s using a photodiode with a responsivity of 0.55 A/W. The TIA consumes 158 mW from a 2.5 V supply and was manufactured in a 0.13-μm SiGe BiCMOS process. Compared with the state of the art, the presented TIA exhibits a similar sensitivity (at both 25 and 40 Gb/s), while exhibiting a low power consumption for the 40-Gb/s operation.

Fast Synchronization 3R Burst-Mode Receivers for Passive Optical Networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed.

DC-coupled burst-mode receiver with high sensitivity, wide dynamic range and short settling time for symmetric 10G-GPONs.

This paper reports a high performance DC-coupled 10Gbit/s optical burst-mode receiver for symmetric 10G-GPONs. The measured receiver sensitivity is −30.0dBm at BER=10⁻³ within a short settling time of 51ns, and a loud/soft ratio wider than 24.0dB.

A 64 Gb/s PAM-4 linear optical receiver

We present a linear optical receiver realized on 130 nm SiGe BiCMOS. Error-free operation assuming FEC is shown at bitrates up to 64 Gb/s (32 Gbaud) with 165mW power consumption, corresponding to 2.578 pJ/bit.

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages.

Multichannel 25 Gb/s Low-Power Driver and Transimpedance Amplifier Integrated Circuits for 100 Gb/s Optical Links

Highly integrated electronic driver and receiver ICs with low-power consumption are essential for the development of cost-effective multichannel fiber-optic transceivers with small form factor. This paper presents the latest results of a two-channel 28 Gb/s driver array for optical duobinary modulation and a four-channel 25 Gb/s TIA array suited for both NRZ and optical duobinary detection. This paper demonstrated that 28 Gb/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Ω, without degrading the signal quality. To the best of our knowledge, this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 × 25 Gb/s TIA shows a good sensitivity of -10.3 dBm average optical input power at 25 Gb/s for PRBS 231-1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process.

A 10Gb/s APD-based linear burst-mode receiver with 31dB dynamic range for reach-extended PON systems.

We present a first high performance APD-based linear burst-mode receiver (BM-RX) with a record wide dynamic range of 31dB. The APD multiplication factor is controlled from burst to burst within 60ns by an on-chip self-generated M-control signal.

Quaternary TDM-PAM as upgrade path of access PON beyond 10Gb/s

A 20 Gb/s quaternary TDM-PAM passive optical network with chirped and non-linear optical transmitters is experimentally demonstrated. The migration from legacy TDM-PONs and the implications of using available 10 Gb/s components are analyzed. We show that a loss budget of 27.3 dB is compatible together with a packet power ratio of 10 dB between loud and soft optical network units.