Joe R. Trogolo

Gate Oxide Leakage and Floating Gate Capacitor Matching Test

Capacitor matching is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. As technologies advance, however, new challenges emerge. In this paper we describe the impact of MOSFET thin gate oxide leakage on the technique. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. In addition, we propose a field MOSFET approach to solve the problem. Since field oxide thickness is typically several thousand Angstroms, gate leakage is negligible. Thick gate oxide MOSFET and Field MOSFET measurement data are compared.

Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.

Impact of Sinter Process and Metal Coverage on Transistor Mismatching and Parameter Variations in Analog CMOS Technology

In this paper, we report detailed studies on the impacts of sinter process and metal coverage on CMOS transistor matching and parameter variability in an analog CMOS technology. Transistor matching and parameter variations with different metal slotting sizes processed at different sinter temperatures have also been studied. It has been found that both metal plating and sinter temperature play critical roles in transistor matching and parameter variation. Metal plating degrades VT and current matching (VT offset ~30 mV, DeltaI/I~18% at moderate inversion and DeltaI/I~3% at strong inversion) significantly at low sinter temperature. Metal slotting array of size 15umX15um with 5um separation over the transistor array has been demonstrated to be very effective in reducing the systematic mismatching. The transistor mismatching improves at higher sinter temperature. Calculated current variations agree well with experimental results.

High speed junction diodes in BiCMOS technologies

Implementation of a very fast high voltage junction diode in a BiCMOS technology is discussed. It is shown that the diode is more than two orders of magnitude faster with almost two orders of magnitude lower stored charge compared to a conventional junction diode in a BiCMOS technology. Using the suggested diode structure, one can achieve the required isolation to the substrate as well as obtain the switching performance close to that of an ideal Schottky diode. It is also possible to integrate this fast switching diode structure into a LDMOS device to help improve the parasitic performance of the LDMOS and increase its switching speed.

1∕f noise in positive-negative-positive (PNP) polycrystalline silicon-emitter bipolar transistors

The origin of 1∕f fluctuations in positive-negative-positive (PNP) polycrystalline silicon-emitter bipolar-junction transistors is described. The interfacial oxide (IFO) at the monosilicon–polycrystalline silicon interface is found to significantly affect the noise behavior. The low-frequency noise originates from two independent fluctuation mechanisms: in the diffusion and tunneling components of the base current noise power spectral density (SIB) and from the diffusion current and carrier number fluctuations in the collector current noise power spectral density (SIC). The Hooge noise parameters for electrons and holes are calculated from the diffusion fluctuation models for SIB and SIC, respectively. Noise measurements on devices with different sizes and different IFO thicknesses indicate that the fluctuations occur in the minority-carrier (electron) tunneling current component of SIB through the IFO. The thickness of the IFO is estimated using this noise model. The tunneling fluctuations dominate over ...

1/f noise in advanced bipolar technologies

The low-frequency noise observed on advanced junction bipolar transistors consist of 1/f noise as well as Random telegraph Signals (RTS). In relatively small emitter-base junction areas, RTS is seen in the spectra which can be differentiated from the typical generation-recombination (gr) noise through time domain analysis. For most cases, the 1/f noise can be modeled primarily with a current noise source in the base SIB. There are cases, however, the noise originates primarily in the collector side due to SIC, which has been neglected in modeling equations. We have designed two different measurement and analysis systems where the effect of SIC and SIB can be differentiated and separately modeled through correlated noise measurements that are performed at the collector and base or collector and emitter. Cross-power spectral density, as well as coherence is used to extract different noise components. Variable temperature low-frequency noise measurements to extract the different components of SIB revealed that the diffusion noise due to mobility fluctuation, fluctuations in the recombination at the surface of the emitter/base depletion region, and fluctuations in the interfacial oxide tunneling barrier height, (and thus the tunneling probability of the carrier) are the components that need to be modeled. The results of the experimental data as well as modeling equations and techniques will be discussed.

Leakage Current and Floating Gate Capacitor Matching Test

Capacitor mismatch is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. In this paper we describe the impact of leakage current on the technique. The leakage can come from, for example, thin gate oxide MOSFETs or high dielectric constant capacitors in advanced technologies. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. Criteria for accurate capacitor systematic and random mismatch characterization are developed, and practical methods of increasing measurement accuracy are discussed.

Comparison of 1/f noise in complementary NPN and PNP polysilicon emitter bipolar transistors

1/f noise was investigated in a complementary polysilicon emitter bipolar process. Noise measurements were carried out for variable base bias resistance (RS) to analyze how the contribution of each noise source changes as RS is varied. Two noise measurement setups were used to identify different noise sources in the transistors: noise from the base current (SIB), collector current (SIC), and internal resistances (SVr). The coherence for transistors measured in both measurement setups were close to unity, implying a single dominant noise source. SIB had the dominant contribution at lower bias currents. In this case, RS was relatively larger than the input resistance of the transistor. Higher current measurements with a smaller RS showed a dominant contribution from SVr. SIB was modeled as a combination of the minority carrier diffusion fluctuations in the monosilicon and polysilicon emitter, and tunneling fluctuations through the interfacial oxide. A combination of the number and diffusion fluctuations of the minority carriers in the base was used to model SIC. It was concluded that mainly originates from the fluctuations in the internal emitter resistance, which was ascribed to the tunneling fluctuations of the majority carriers through the interfacial oxide.

1/f noise and RTS in advanced bipolar technologies

The low-frequency noise observed on advanced junction bipolar transistors consist of 1/f noise as well as Random telegraph Signals (RTS). In relatively small emitter-base junction areas, RTS is seen in the spectra which can be differentiated from the typical generation-recombination (gr) noise through time domain analysis. For most cases, the 1/f noise can be modeled primarily with a current noise source in the base SIB. There are cases, however, the noise originates primarily in the collector side due to SIC, which has been neglected in modeling equations. We have designed two different measurement and analysis systems where the effect of SIC and SIB can be differentiated and separately modeled through correlated noise measurements that are performed at the collector and base or collector and emitter. Cross-power spectral density, as well as coherence is used to extract different noise components. Variable temperature low-frequency noise measurements to extract the different components of SIB revealed that the diffusion noise due to mobility fluctuation, fluctuations in the recombination at the surface of the emitter/base depletion region, and fluctuations in the interfacial oxide tunneling barrier height, (and thus the tunneling probability of the carrier) are the components that need to be modeled. The results of the experimental data as well as modeling equations and techniques will be discussed.