Dan M. Mosher

off -State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.

Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent R/sub sp/ vs BV performance

This paper discusses modeling and experimental development of self-aligned RESURF 60 V rated LDMOS power MOSFETs. The goals of this work were to provide state-of-the-art BV vs. R/sub sp/ performance RESURF devices using existing fabrication techniques capable of high current conduction. The devices were fabricated in a production environment with an additional RESURF implant added to the process. Best performance reported is BV=69 V, and R/sub sp/=0.82 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V which is the best to our knowledge in this voltage range. Large (18 m/spl Omega/) devices were demonstrated with linear performance up to 60 and 100 A @V/sub gs/=10 V and 15 V respectively. Thick third level metal was used to reduce surface interconnect debiasing.

Multi-probe Two-Dimensional Mapping of Off-State Degradation in DeNMOS Transistors: How and Why Interface Damage Predicts Gate Dielectric Breakdown

Through a combination of measurements techniques, we show that the generation of both interface and bulk traps during off-state stress in drain extended NMOS transistors are driven by the same physical mechanism and as such have similar time and voltage dependencies. We also show that the peak interface damage location (obtained from charge pumping measurement) along with asymmetric percolation model successfully interpret the observed Weibull slope of dielectric breakdown during off-state stress. Our analysis suggests the intriguing possibility of replacing time consuming off-state TDDB measurements by simple charge pumping analysis.