Joel Darnauer

Interchangeable pin routing with application to package layout

Many practical routing problems such as BGA, PGA, pin redistribution and test fixture routing involve routing with interchangeable pins. These routing problems, especially package layout, are becoming more difficult to do manually due to increasing speed and I/O. Currently, no commercial or university router is available for this task. In this paper, we unify these different problems as instances of the interchangeable pin routing (IPR) problem, which is NP-complete. By representing the solution space with flows in a triangulated routing network instead of grids, we developed a min-cost max-flow heuristic considering only the most important cuts in the design. The heuristic handles multiple layers, prerouted nets, and all-angle, octilinear or rectilinear wiring styles. Experiments show that the heuristic is very effective on most practical examples. It had been used to route industry designs with thousands of interchangeable pins.

A field programmable multi-chip module (FPMCM)

Multi-chip module (MCM) packaging can reduce the cost and increase the utility of field programmable systems. We are currently developing a first generation field programmable multi-chip module (FPMCM) as a test vehicle for a particular MCM technology. We present the advantages of MCM for field programmable systems and develop analytical models for estimating the capacity of FPMCM architectures based on Rents rule. These models are used to generate the architecture of our first generation prototype which employs smaller FPGA die and a mixture of direct and switched interconnect. We conclude with a discussion of the challenges and opportunities that FPMCMs face.<<ETX>>

Fast pad redistribution from periphery-IO to area-IO

The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze the even wiring distribution (EWD) routing heuristic and show that it produces designs whose critical wire density is no greater that /spl radic/2 times the best possible design. Then, we employ the bound on EWD to establish a surprisingly non-monotonic relationship between bump pitch and design routability, and present our implementation of a design system that employs these principles.<<ETX>>

A silicon-on-silicon field programmable multichip module (FPMCM) integrating FPGA and MCM technologies

Multichip module technology can dramatically increase the capability of field programmable logic devices (FPLDs) and field programmable systems (FPS). We present the special advantages that MCMs offer FPLDs and the design of our first-generation field programmable multichip module (FPMCM). Our prototype is the first silicon-on-silicon FPMCM and has a maximum capacity of 40 K gates and 256 user IO, achieving a factor of four increase in capacity over the FPLD family with which it was designed. Our FPMCM has bean demonstrated in a system that can deliver 200 MOPs of computing power for image processing applications. FPMCMs can cost-effectively deliver 4-8 times the capacity of the largest FPLDs and provide even larger reductions in the area of PCB-based field programmable systems. The upper capacity limits for FPMCM are determined mainly by the cost and defect density of the substrate technology. As CMOS processes move into the deep-submicron range, FPMCMs will even faster and denser substrates. >

Field programmable multi-chip module (FPMCM)-an integration of FPGA and MCM technology

Multichip module technology can be used to dramatically increase the capability and performance of field programmable gate arrays (FPGAs) and the field programmable systems (FPS) that they are a part of. After an analysis of the key advantages that MCM technology has for FPGAs, we present the design of our first-generation silicon-on-silicon field programmable multi-chip module (FPMCM), analyze its limitations, and present some lessons learned in the development process. We conclude with a comparison of MCM-C and MCM-D technology for this application and suggest that the case for MCM-D for FPMCMs is most compelling when MCM-D is considered as a doorway to active substrate and chip-on-chip technologies.

Tradeoffs in chip and substrate complexity and cost for field programmable multichip modules

Field programmable MCMs (FPMCMs) can be used to improve the cost-effectiveness of large logic emulation and reconfigurable computing systems. In this paper, we consider two MCM-D based FPMCMs developed at UCSC to illustrate the impact of chip size on substrate wiring density and module cost. We then present a simple model of an idealized FPMCM that can be used to generate relative cost and yield estimates for different architectures. Architectural implications of this model are presented including the optimal number of chips, effect of chip bonding technology on overall cost, and limits to the integration factor for MCMs. We then briefly consider how increasing CMOS density, and innovative technologies like chip-on-chip and chip stacking might affect substrate density in the near future.

A 1024-pin plastic ball grid array for flip chip die

Described in this paper is a 1024-pin ball grid array package (BGA) that contains an area array die flip-chip mounted to a silicon transposer. The transposer, which fans the area array to two rows of pads on its periphery, is wire bonded to a printed circuit board substrate. Mechanical and electrical design considerations of the BGA are discussed, as well as the results of SPICE models.<<ETX>>