Johan Hendrik Klootwijk

Plasma and Thermal ALD of Al2O3 in a Commercial 200 mm ALD Reactor

The deposition of Al 2 O 3 by remote plasma atomic layer deposition (ALD) in the Oxford Instruments FlexAL reactor was studied and compared with results from thermal ALD in the same reactor. Trimethylaluminum [Al(CH 3 ) 3 ] was used as the metal precursor and O 2 plasma and H 2 O were used as oxidizing agents for the plasma and thermal processes, respectively. For remote plasma ALD with a total cycle time of 4 s, the growth per cycle decreased monotonically with substrate temperature, from 1.7 A/cycle at 25°C to 1.0 A/cycle at 300°C. This growth per cycle was consistently higher than that obtained for thermal ALD. For the latter a maximum growth per cycle of ∼ 1.0 A/cycle was found at 200°C. The film properties investigated were nearly independent of oxidant source for temperatures between 100 and 300°C, with a slightly higher mass density for the remote plasma ALD Al 2 O 3 films. Films deposited at 200 and 300°C were stoichiometric with a mass density of 3.0 g/cm 3 and low C (< 1 atom %) and H (<3 atom %) contents. At lower substrate temperatures, oxygen-rich films were obtained with a lower mass density and higher H-content. Remote plasma ALD produced uniform Al 2 O 3 films with nonuniformities of less than ±2% over 200 mm diam substrates. Excellent conformality was obtained for films deposited in macropores with an aspect ratio of ∼8 (2.0-2.5 μm diam). Preliminary results on electrical properties of remote plasma deposited films showed high dielectric constants of 7.8 and 8.9 for as-deposited and forming gas annealed Al 2 O 3 , respectively.

Ultrahigh Capacitance Density for Multiple ALD-Grown MIM Capacitor Stacks in 3-D Silicon

ldquoTrenchrdquo capacitors containing multiple metal-insulator-metal (MIM) layer stacks are realized by atomic-layer deposition (ALD), yielding an ultrahigh capacitance density of 440 at a breakdown voltage VDB > 6 V. This capacitance density on silicon is at least 10times higher than the values reported by other research groups. On a silicon substrate containing high-aspect-ratio macropore arrays, alternating MIM layer stacks comprising high-k Al2O3dielectrics and TiN electrodes are deposited using optimized ALD processing such that the conductivity of the TiN layers is not attacked. Ozone annealing subsequent to each Al2O3 deposition step yields significant improvement of the dielectric isolation and breakdown properties.

Deposition of TiN and HfO2 in a commercial 200mm remote plasma atomic layer deposition reactor

The authors describe a remote plasma atomic layer deposition reactor (Oxford Instruments FlexAL™) that includes an inductively coupled plasma source and a load lock capable of handling substrates up to 200mm in diameter. The deposition of titanium nitride (TiN) and hafnium oxide (HfO2) is described for the combination of the metal-halide precursor TiCl4 and H2–N2 plasma and the combination of the metallorganic precursor Hf[N(CH3)(C2H5)]4 and O2 plasma, respectively. The influence of the plasma exposure time and substrate temperature has been studied and compositional, structural, and electrical properties are reported. TiN films with a low Cl impurity content were obtained at 350°C at a growth rate of 0.35A∕cycle with an electrical resistivity as low as 150μΩcm. Carbon-free (detection limit <2at.%) HfO2 films were obtained at a growth rate of 1.0A∕cycle at 290°C. The thickness and resisitivity nonuniformity was <5% for the TiN and the thickness uniformality was <2% for the HfO2 films as determined over 200mm wafers.The authors describe a remote plasma atomic layer deposition reactor (Oxford Instruments FlexAL™) that includes an inductively coupled plasma source and a load lock capable of handling substrates up to 200mm in diameter. The deposition of titanium nitride (TiN) and hafnium oxide (HfO2) is described for the combination of the metal-halide precursor TiCl4 and H2–N2 plasma and the combination of the metallorganic precursor Hf[N(CH3)(C2H5)]4 and O2 plasma, respectively. The influence of the plasma exposure time and substrate temperature has been studied and compositional, structural, and electrical properties are reported. TiN films with a low Cl impurity content were obtained at 350°C at a growth rate of 0.35A∕cycle with an electrical resistivity as low as 150μΩcm. Carbon-free (detection limit <2at.%) HfO2 films were obtained at a growth rate of 1.0A∕cycle at 290°C. The thickness and resisitivity nonuniformity was <5% for the TiN and the thickness uniformality was <2% for the HfO2 films as determined over 20...

Deposition of TiN and TaN by Remote Plasma ALD for Cu and Li Diffusion Barrier Applications

TaN and TiN films were deposited by remote plasma atomic layer deposition (ALD) using the combinations of Ta[N(CH 3 ) 2 ] 5 precursor with H 2 plasma and TiCl 4 precursor with H 2 -N 2 plasma, respectively. Both the TaN and TiN films had a cubic phase composition with a relatively low resistivity (TaN: 380 μΩ cm; TiN: 150 μΩ cm). Dissimilar from the TiN properties, the material properties of the TaN films were found to depend strongly on the plasma exposure time. Preliminary tests on planar substrates were carried out revealing the potential of the TaN and TiN films as Cu and Li diffusion barriers in through-silicon via and silicon-integrated thin-film battery applications, respectively. For the specific films studied, it was found that TiN showed better barrier properties than TaN for both application areas. The TiN films were an effective barrier to Cu diffusion and had no Cu diffusion for anneal temperatures up to 700°C. The TiN films showed low Li intercalation during electrochemical charging and discharging.

Merits and limitations of circular TLM structures for contact resistance determination for novel III-V HBTs

This paper discusses merits and limitations of CTLM (Circular Transfer Length Method) contact resistance assessment test structures. Requiring just one lithography step, these structures prove to be a simple yet very powerful tool in characterizing and optimizing the contact resistances for III-V based heterojunction bipolar transistors (HBTs).

Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge/sub 0.3/Si/sub 0.7/) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, /spl phi//sub B/, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q/sub bd/) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

Dielectric Properties of Thermal and Plasma-Assisted Atomic Layer Deposited Al2O3 Thin Films

A comparative electrical characterization study of aluminum oxide (Al2O3) deposited by thermal and plasma-assisted atomic layer depositions (ALDs) in a single reactor is presented. Capacitance and leakage current measurements show that the Al2O3 deposited by the plasma-assisted ALD shows excellent dielectric properties, such as better interfaces with silicon, lower oxide trap charges, higher tunnel barrier with aluminum electrode, and better dielectric permittivity (k = 8.8), than the thermal ALD Al2O3. Remarkably, the plasma-assisted ALD Al2O3 films exhibit more negative fixed oxide charge density than the thermal ALD Al2O3 layers. In addition, it is shown that plasma-assisted ALD Al2O3 exhibits negligible trap-assisted (Poole-Frenkel) conduction unlike the thermal ALD Al2O3 films, resulting in higher breakdown electric fields than the thermal ALD prepared films

ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs

This paper reviews the options of using Atomic Layer Deposition (ALD) in passive and heterogeneous integration. The miniaturization intended by both integration schemes aim at Si-based integration for the former and at die stacking in a compact System-in-Package for the latter. In future Si-based integrated passives a next miniaturization step in trench capacitors requires the use of multiple ‘classical’ MOS layer stacks and the use of so-called high-k dielectrics (based on HfO2, etc.) and novel conductive layers like TiN, etc. to compose MIS and MIM stacks in ‘trench’ and ‘pore’ capacitors with capacitance densities exceeding 200 nF/mm 2 . One of the major challenges in realizing ultrahigh-density trench capacitors is to find an attractive pore lining and filling fabrication technology at reasonable cost and reaction rate as well as low temperature (for back-end processing freedom). As the deposition for the dielectric and conductive layers should be highly uniform, step-conformal and lowtemperature (≤ 400 °C), ALD is an enabling technology here, by virtue of the self-limiting mechanism of this layer-by-layer deposition technique. This article discusses first a few examples of LPCVD deposition of conventional MOS layers with ONO-dielectrics and in situ doped polycrystalline silicon, both as single layers and multilayer stacks. In addition, a few options for ALD deposition of thin dielectric and conductive layers (e.g. HfO2- and TiN-based) will be discussed. The silicon substrates that were used contained high aspect ratio (≥ 20) features with cross-section and spacing of the order of 1 µm.

Deposited inter-polysilicon dielectrics for nonvolatile memories

Deposited instead of thermally grown oxides were studied to form very high-quality inter-polysilicon dielectric layers for embedded nonvolatile memory application. It was found that by optimizing the microstructure, i.e., texture and morphology of the polysilicon layers, and by optimizing the post dielectric deposition anneal, very high-quality dielectric layers can be obtained. In this paper it is shown on simple capacitor structure level and full EEPROM device level that the electrical properties of interpoly dielectric layers can be improved tremendously by using deposited dielectric layers with additional rapid thermal anneal. Typical results are: a high charge-to-breakdown (Q/sub BD//spl ap/25 C/cm/sup 2/), low leakage currents and decreased charge trapping during constant current stress. An additional advantage is the low thermal budget, which is very attractive for embedded applications. However, results depend on the polysilicon preparation, dielectric type and RTP anneal environment. From electrical evaluation it appeared that even for deposited dielectric layers the influence of polysilicon surface roughness and corners is considerable. The optimized combination of flat polysilicon layers, deposited inter-polysilicon dielectric and additional optimized rapid thermal anneal have been applied in full EEPROM devices. Cycling over one million cycles was possible, which indicates an endurance improvement by a factor of 10.

Up-Scaling Graphene Electronics by Reproducible Metal-Graphene Contacts

Chemical vapor deposition (CVD) of graphene on top of metallic foils is a technologically viable method of graphene production. Fabrication of microelectronic devices with CVD grown graphene is commonly done by using photolithography and deposition of metal contacts on top of the transferred graphene layer. This processing is potentially invasive for graphene, yields large spread in device parameters, and can inhibit up-scaling. Here we demonstrate an alternative process technology in which both lithography and contact deposition on top of graphene are prevented. First a prepatterned substrate is fabricated that contains all the device layouts, electrodes and interconnects. Then CVD graphene is transferred on top. Processing parameters are adjusted to yield a graphene layer that adopts the topography of the prepatterned substrate. The metal-graphene contact shows low contact resistances below 1 kΩ μm for CVD graphene devices. The conformal transfer technique is scaled-up to 150 mm wafers with statistically similar devices and with a device yield close to unity.