Jean Peperstraete

Cycle-static dataflow

We present cycle-static dataflow (CSDF), which is a new model for the specification and implementation of digital signal processing algorithms. The CSDF paradigm is an extension of synchronous dataflow that still allows for static scheduling and, thus, a very efficient implementation of an application. In comparison with synchronous dataflow, it is more versatile because it also supports algorithms with a cyclically changing, but predefined, behavior. Our examples show that this capability results in a higher degree of parallelism and, hence, a higher throughput, shorter delays, and less buffer memory. Moreover, they indicate that CSDF is essential for modelling prescheduled components, like application-specific integrated circuits. Besides introducing the CSDF paradigm, we also derive necessary and sufficient conditions for the schedulability of a CSDF graph. We present and compare two methods for checking the liveness of a graph. The first one checks the liveness of loops, and the second one constructs a single-processor schedule for one iteration of the graph. Once the schedulability is tested, a makespan optimal schedule on a multiprocessor can be constructed. We also introduce the heuristic scheduling method of our graphical rapid prototyping environment (GRAPE).

Cyclo-static data flow

The high sample-rates involved in many DSP-applications, require the use of static schedulers wherever possible. The construction of static schedules however is classically limited to applications that fit in the synchronous data flow model. In this paper we present cyclo-static data flow as a model to describe applications with a cyclically changing behaviour. We give both a necessary and sufficient condition for the existence of a static schedule for a cyclo-static data flow graph and show how such a schedule can be constructed. The example of a video encoder is used to illustrate the importance of cyclo-static data flow for real-life DSP-systems.

Grape-II: a system-level prototyping environment for DSP applications

We propose a rapid-prototyping setup to minimize development cost and a structured-prototyping methodology to reduce programming effort. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and field-programmable gate arrays (FPGAs) linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project. Our Graphical Rapid Prototyping Environment (Grape-II) automates the prototyping methodology for these hardware systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. Grape-II has been used successfully in three real-world DSP applications. >

GRAPE: a CASE tool for digital signal parallel processing

The use of computer-aided software engineering (CASE) tools for stream-oriented real-time digital signal processing (DSP) applications is discussed. These applications are characterized by a continuous stream of data samples or a continuous stream of blocks of data samples arriving at the processing facility at time instances completely determined by the outside world. An overview of existing development tools for DSP is given. The CASE tool GRAPE (graphical programming environment), which allows for easy programming, compiling, debugging and evaluating of high-frequency real-time DSP systems, is presented. Its main distinctive feature is that the tool spans the whole design process, ranging from analysis over simulation and emulation up to implementation on general-purpose DSP multiprocessors or integration on an application-specific integrated circuit (ASIC). The DSP multiprocessor can be the target hardware or can be used for real-time emulation or accelerated simulation of an ASIC.<<ETX>>

Hardware-software codesign with GRAPE

GRAPE-II (Graphical Rapid Prototyping Environment-II) is a hardware-software codesign environment for the real-time functional emulation of synchronous DSP systems. It allows one to specify the applications data dependency graph in a target-machine-independent way. After specifying the heterogeneous target machines architecture, it estimates the resources needed by each application subtask. Based on these requirements, it assigns the subtasks to specific target devices at compile-time, be they processors or FPGAs, establishes routing paths and determines a static schedule. It generates a main shell for each target device and generates intra-device and inter-device communication code. After downloading the executable images on to the target machine, it allows the designer to modify end-user controls and application settings at run-time. This paper situates the tool in the application design cycle, explains GRAPE-IIs design flow and shows the advantages of hardware-software codesign by evaluating the achievable sampling frequency for a small example application.

Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

The paper presents an algorithm to determine the close-to-smallestpossible data buffer sizes for arbitrary synchronous dataflow (SDF) applications, such that we can guarantee the existenceof a deadlock free schedule. The presented algorithm fits inthe design flow of GRAPE, an environment for the emulation andimplementation of digital signal processing (DSP) systems onarbitrary target architectures, consisting of programmable DSPprocessors and FPGAs. Reducing the size of data buffers is ofhigh importance when the application will be mapped on FieldProgrammable Gate Arrays (FPGA), since register resources arerather scarce.

Cycle-static dataflow: model and implementation

Cycle-static dataflow (CSDF) is used for specifying digital signal processing algorithms with a cyclically changing, but predefined, behavior. Unlike other models for such applications, CSDF allows for static scheduling and hence a very efficient implementation. We review the CSDF paradigm and present the scheduling approach for CSDF graphs that is currently implemented in the Graphical Rapid Prototyping Environment GRAPE.<<ETX>>

Geometric parallelism and cyclo-static data flow in GRAPE-II

Describes two novel features that are supported in GRAPE-II (Graphical RApid Prototyping Environment): geometric parallelism and cyclo-static data flow. GRAPE-II is intended as a system level tool for the rapid prototyping of digital signal processing (DSP) applications on multiprocessors. GRAPE-II fully supports code generation for multi-rate and asynchronous DSP applications on heterogeneous target multiprocessors. The first feature detailed in the paper, geometric parallelism, allows the programmer to efficiently specify data parallel operations, where multiple identical functions operate on different data sets. The second feature, cyclo-static data flow, enables the specification of cyclicly changing data dependencies, while still leading to static schedules.<<ETX>>

Static scheduling of multi-rate and cyclo-static DSP-applications

The high sample-rates involved in many DSP-applications, require the use of static schedulers wherever possible. The construction of static schedules however is classically limited to applications that fit in the synchronous data flow model. In this paper we present cyclo-static data flow as a model to describe applications with a cyclically changing behaviour and build a static schedule for them as well. We also propose a new scheduling method for both multi-rate and cyclo-static applications. Characteristic for this method is that the graph does not need to be transformed into a single-rate equivalent. The new scheduling technique has been implemented in GRAPE-II (Graphical RApid Prototyping Environment).

Cyclo-dynamic dataflow

We present cyclo dynamic data flow (CDDF), a new data flow model for real time digital signal processing (DSP) applications. CDDF is an extension of cyclo static dataflow (CSDF) (G. Bilsen et al.; M. Engels et al., 1994) that keeps the interesting properties like analyzability and efficient compile time scheduling, while introducing data dependent control flow to improve the expressivity. The semantics are constructed such that extra knowledge about the internals of the actors, which is known to the programmer, can be expressed both in a natural way, and in a syntax that can be analyzed by automatic tools. We describe the proposed model in the context of already existing data flow languages, demonstrate its schedulability and its improved analyzability as compared to the Boolean data flow model (J.T. Buck, 1993).