Johanes Swenberg

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using NH3 anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide NH3 anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of NH3 anneal is related to higher N incorporation into SiO2 bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to NH3 anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.

Is Selective Cvd an Improvement for the Titanium Silicide Process in Sub-Quarter Micron Technology? A Phase Formation Study Using X-Ray Diffraction

The C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 10 6 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl 4 and SiH 4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.