Theresa Kramer Guarini

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using NH3 anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide NH3 anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of NH3 anneal is related to higher N incorporation into SiO2 bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to NH3 anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.

Nitric oxide rapid thermal nitridation for Flash memory applications

Rapid thermal annealing in nitric oxide (RTNO) has long been used for the formation of ultrathin silicon oxynitride gate dielectrics. Nitric oxide (NO) furnace anneals are used in the formation of floating gate Flash memory transistor tunnel oxides. Nitrogen is thus, incorporated to improve the oxide reliability during program/erase cycling endurance and data retention. We present here a study of rapid thermal annealing and oxide growth in nitric oxide using Applied Materials single-wafer rapid thermal process (RTP) that enables the RTNO anneal to operate at higher temperatures compared to furnace, thereby allowing two times greater incorporation of nitrogen at the silicon/silicon dioxide interface. At 1200°C, a greater than 11% peak interface nitrogen concentration as measured by secondary ion mass spectroscopy (SIMS) in a 75 Angstrom SiON film is achieved. Reliability testing using a floating gate flash memory capacitor with minority carrier source (implants) test vehicle shows that this increase in the peak interface nitrogen results in an improvement in the tunnel oxides program/erase cycling endurance and data retention. For future memory devices, for example 3D memory devices, the use of direct RTNO oxide growth for dielectric formations is possible. In this case, higher temperatures allow the growth of thicker oxides in pure NO at 1200°C, with greater nitrogen incorporation.

Ultrathin SiO 2 interface layer growth

A variety of processes based on radical oxidation (N2O/H2) and spike RTO are investigated in this study to grow ultrathin SiO2 layers. Their process space is mapped out to cover regimes of interest for gate-last or gate-first integration of high k dielectrics with metal gates. Applieds Centura RTP chamber is found to be readily compatible with the requirements associated with 22/20nm CMOS technology.

Integrated modeling platform for High-k/alternate channel material heterostructure stacks

To study the High-k dielectrics on alternate semiconductor materials for transistors a modeling platform has been developed which implements a faster 1D Schrodinger-Poisson along with trap models. A fitting algorithm is used for the extraction of trap profiles which fits the model capacitance/admittance to the measurements in the least square sense. The extraction is illustrated on a subnanometer EOT HfO2/SiGe/Si heterostructure stack.