Robert L. Sankman

Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect

The EMIB dense MCP technology is a new packaging paradigm that provides localized high density interconnects between two or more die on an organic package substrate, opening up new opportunities for heterogeneous on-package integration. This paper provides an overview of EMIB architecture and package capabilities. First, EMIB is compared with other approaches for high density interconnects. Some of the inherent advantages of the technology, such as the ability to cost effectively implement high density interconnects without requiring TSVs, and the ability to support the integration of many large die in an area much greater than the typical reticle size limit are highlighted. Next, the overall EMIB architecture envelope is discussed along with its constituent building blocks, the package construction with the embedded bridge, die to package interconnect features. Next, the EMIB assembly process is described at a high level. Finally, high bandwidth signaling between the die is discussed and the link bandwidth envelope is quantified.

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.

Low cost flip chip package design concepts for high density I/O

The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal of the highly resistive and inductive wire bonds, high-speed buses achieve well-controlled characteristic impedance for signal wave propagation and lower impedance for the power delivery network. However, a disadvantage of flip chip packaging is its lower input/output (I/O) routing density when compared to wire bond packaging. To meet the high I/O count for certain products, innovative flip chip bump patterns and creative routing options are needed. This paper will outline some innovative package design concepts on both die to package, defined as level 1 interconnect, and package to motherboard (MB), defined as level 2 interconnect, to increase the I/O signal routing density without increasing the package or MB cost.

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS

A wireless sensor node (WSN) integrates a 0.79mm2 near-threshold voltage (NTV) 32-bit Intel Architecture (IA) microcontroller (MCU) in 14nm tri-gate CMOS, along with solar cell, energy harvester, flash memory, sensors and Bluetooth Low Energy (BLE) radio, to enable always-on always-sensing (AOAS) and advanced edge computing capabilities in Internet-of-Things (IoT) systems. The MCU features four independent voltage-frequency islands (VFI), a low-leakage SRAM array, an on-die oscillator clock source capable of operating at sub-threshold voltage, power gating and multiple active/sleep states, managed by an integrated power management unit (PMU). The MCU operates across a wide frequency (voltage) range of 297MHz (1V) to 0.5MHz (308mV), and achieves a peak energy efficiency of 17pJ/cycle at an optimum supply voltage (VOPT) of 370mV, operating at 3.5MHz. The WSN, powered by a solar cell, demonstrates sustained MHz AOAS operation, consuming only 360μW.

Advances and Challenges in Flip-Chip Packaging

The role of semiconductor packaging has evolved from space transformation and environmental protection, to becoming an important enabler for silicon and system performance. This paper examines some of the advances in flip-chip packaging as an enabler of power delivery and power removal using a microprocessor as an example. In addition, the role of the package as an enabler of system I/O performance and silicon back-end reliability will be examined