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Dive into the research topics where Johannes F. C. M. Verhoeven is active.

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Featured researches published by Johannes F. C. M. Verhoeven.


Microelectronic Engineering | 2000

High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom; R. J. G. Elfrink; Johannes F. C. M. Verhoeven; J. van den Meerakher; Frans Holthuysen

A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of @mm deep with a width and pitch of a few @mm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 @mF. The specific capacitance was as high as 100 nF/mm^2.


Journal of The Electrochemical Society | 2000

Etching of Deep Macropores in 6 in. Si Wafers

J. E. A. M. van den Meerakker; R. J. G. Elfrink; F. Roozeboom; Johannes F. C. M. Verhoeven

The process of photoanodic etching of deep pores in lightly doped n - -Si wafers was investigated. On a 6 in, wafer, more than 1 billion pores, regularly distributed over the wafer in a hexagonal array with a pitch of 3.5 μm, were obtained using an electrolytic back contact. The diameter of the pores was about 2 μm and depths up to 400 μm could be achieved. Kinetic experiments revealed that the etching process was diffusion controlled in a solution containing HF, H 2 O, and ethanol. Electrochemical experiments showed that H 2 evolution took place at the back side of the Si wafer and that H 2 and O 2 evolved at the Pt cathode and anode, respectively.


MRS Proceedings | 2003

High-Density, Low-loss MOS Decoupling Capacitors integrated in a GSM Power Amplifier

F. Roozeboom; Antonius L. A. M. Kemmeren; Johannes F. C. M. Verhoeven; E. van den Heuvel; H. Kretschman; Tomas Fric

High-density MOS capacitors have been fabricated with ∼ 30 nF/mm 2 specific capacitance on highly-doped Si-wafers with arrays of macropores with ∼ 2 μm diameter. Using the Bosch process [1] these pores were dry-etched to depths of ∼ 30 μm or more. The enlarged Si-surface thus obtained serves as a substrate for capacitors fabricated by fully MOS-compatible processing. Wafers were fabricated with a top electrode of poly-Si and Al and ‘ONO’ (i.e. oxide / nitride / oxide) dielectric stacks showing 7–10 MV/cm electrical breakdown field and leakage 2 @ 20 V. These wafers were thinned to 380 μm and sawn into dies, representing 40 nF capacitors. Typically low loss factors such as ESR 2 O 3 or laminate substrate as supply-line decoupling capacitors in complete GSM power amplifier test modules. RF decoupling and transmission were measured and compared to identical test modules with conventional discrete ceramic capacitors. The MOS capacitors showed very efficient decoupling, resulting in superior signal stability as measured in the 0 – 1 GHz range (less noisy, free from oscillations). The new capacitor is very suitable for integrated decoupling purposes, e.g. supply-line decoupling in RF wireless communication and analog and mixed-signal systems.


Archive | 1989

Method of manufacturing a semiconductor device having an SOI structure using selectable etching

Alfred H. Van Ommen; Johanna M. L. Mulder; Johannes F. C. M. Verhoeven


Archive | 2006

Integrated capacitor arrangement for ultrahigh capacitance values

F. Roozeboom; Johan Hendrik Klootwijk; Antonius L. A. M. Kemmeren; Derk Reefman; Johannes F. C. M. Verhoeven


Archive | 2003

Method of manufacturing nanowires and electronic device

Erik P. A. M. Bakkers; F. Roozeboom; Johannes F. C. M. Verhoeven; Paul Van Der Sluis


Archive | 1988

Improved method of manufacturing a semiconductor device of the "semiconductor on insulator" type

Elizabeth Maria Leon Alexander; Jan Haisma; Theodorus Martinus Michielsen; Johannes W. A. Van Der Velden; Johannes F. C. M. Verhoeven


The International journal of microcircuits and electronic packaging | 2001

High-density, low-loss MOS capacitors for integrated RF decoupling

F. Roozeboom; R. J. G. Elfrink; Th. G. S. M. Rijks; Johannes F. C. M. Verhoeven; Antonius L. A. M. Kemmeren; J. E. A. M. van den Meerakker


Materials Science in Semiconductor Processing | 2001

The influence of polysilicon gate morphology on dopant activation and deactivation kinetics in deep-submicron CMOS transistors

F.N. Cubaynes; P.A. Stolk; Johannes F. C. M. Verhoeven; F. Roozeboom; P.H. Woerlee


Archive | 1984

Method of manufacturing a pattern of conductive material

P.H. Woerlee; Johannes F. C. M. Verhoeven

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