John A. Carlin

Impact of GaAs buffer thickness on electronic quality of GaAs grown on graded Ge/GeSi/Si substrates

Minority carrier lifetimes and interface recombination velocities for GaAs grown on a Si wafer using compositionally graded GeSi buffers have been investigated as a function of GaAs buffer thickness using monolayer-scale control of the GaAs/Ge interface nucleation during molecular beam epitaxy. The GaAs layers are free of antiphase domain disorder, with threading dislocation densities measured by etch pit density of 5×105–2×106 cm−2. Analysis indicates no degradation in either minority carrier lifetime or interface recombination velocity down to a GaAs buffer thickness of 0.1 μm. In fact, record high minority carrier lifetimes exceeding 10 ns have been obtained for GaAs on Si with a 0.1 μm GaAs buffer. Secondary ion mass spectroscopy reveals that cross diffusion of Ga, As, and Ge at the GaAs/Ge interface formed on the graded GeSi buffers are below detection limits in the interface region, indicating that polarity control of the GaAs/Ge interface formed on GeSi/Si substrates can be achieved.

SiGe-free strained Si on insulator by wafer bonding and layer transfer

SiGe-free strained Si on insulator substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed Si0.68Ge0.32 graded layers. Raman spectroscopy shows that the 49-nm thick strained Si on insulator structure maintains a 1.15% tensile strain even after SiGe layer removal. The strain in the structure is thermally stable during 1000 °C anneals for at least 3 min, while more extreme thermal treatments at 1100 °C cause slight film relaxation. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator forms an ideal platform for future generations of Si-based microelectronics.

High minority-carrier lifetimes in GaAs grown on low-defect-density Ge/GeSi/Si substrates

A high bulk minority-carrier lifetime in GaAs grown on Si-based substrates is demonstrated. This was achieved by utilizing a step-graded Ge/GeSi buffer (threading dislocation density 2×106 cm−2) grown on an offcut (001) Si wafer, coupled with monolayer-scale control of the GaAs nucleation to suppress antiphase domains. Bulk minority-carrier lifetimes (τp) were measured using room-temperature time-resolved photoluminescence applied to a series of Al0.3Ga0.7As/GaAs/Al0.3Ga0.7As double-heterojunction structures doped n=1.1×1017 cm−3 with GaAs thicknesses of 0.5, 1.0, and 1.5 μm. A lifetime τp=7.7 ns was determined for GaAs grown on Si. The extracted interface recombination velocity of 3.9×103 cm/s is comparable to recombination velocities found for Al0.3Ga0.7As/GaAs interfaces grown on both GaAs and Ge wafers, indicating that the crosshatch surface morphology characteristic of strain-relaxed Ge/GeSi surfaces does not impede the formation of high-electronic-quality interfaces. These results hold great promise...

High efficiency GaAs-on-Si solar cells with high V/sub oc/ using graded GeSi buffers

Single junction AlGaAs/GaAs and InGaP/GaAs solar cells and test structures have been grown by molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD), respectively, on Si wafers coated with compositionally-graded GeSi buffers. The combination of controlled strain relaxation within the GeSi buffer and monolayer-scale control of the Ill-V layer nucleation is shown to reproducibly generate minority carrier lifetimes exceeding 10 nanoseconds within GaAs overlayers. The III-V layers are free of long-range antiphase domain disorder, with threading dislocation densities in the high-10/sup 5/ cm/sup -2/ range, consistent with the low residual dislocation density in the Ge cap of the graded buffer structure. Single junction GaAs cells grown by both MBE and MOCVD on the Ge/GeSi/Si substrates demonstrated high V/sub oc/ values for GaAs cells grown on Si. Record V/sub oc/ values for MOCVD-grown single junction InGaP/GaAs cells exceeded 980 mV (AMO) with fill factors of 0.79. Additionally, external quantum efficiency data indicates no degradation in carrier collection from GaAs homoepitaxial cells for current single-junction cell designs grown by MBE. Based on these results, cell efficiencies in excess of 18.5% under AM0 conditions should be attainable with cell designs demonstrating state of the art J/sub sc/ values. Such cell performance demonstrates the potential and viability of graded GeSi buffers for the development of Ill-V cells on Si wafers.

Nucleation-related defect-free GaP/Si(100) heteroepitaxy via metal-organic chemical vapor deposition

GaP/Si heterostructures were grown by metal-organic chemical vapor deposition in which the formation of all heterovalent nucleation-related defects (antiphase domains, stacking faults, and microtwins) were fully and simultaneously suppressed, as observed via transmission electron microscopy (TEM). This was achieved through a combination of intentional Si(100) substrate misorientation, Si homoepitaxy prior to GaP growth, and GaP nucleation by Ga-initiated atomic layer epitaxy. Unintentional (311) Si surface faceting due to biatomic step-bunching during Si homoepitaxy was observed by atomic force microscopy and TEM and was found to also yield defect-free GaP/Si interfaces.

GaAs

Monolithic, epitaxial, series-connected GaAs0.75P0.25/Si dual-junction solar cells, grown via both molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD), are reported for the first time. Fabricated test devices for both cases show working tandem behavior, with clear voltage addition and spectral partitioning. However, due to thermal budget limitations in the MBE growth needed to prevent tunnel junction failure, the MBE-grown GaAs0.75P0.25 top cell was found to be lower quality than the equivalent MOCVD-grown device. Additionally, despite the reduced thermal budget, the MBE-grown tunnel junction exhibited degraded behavior, further reducing the overall performance of the MBE/MOCVD combination cell. The all-MOCVD-grown structure displayed no such issues and yielded significantly higher overall performance. These initial prototype cells show promising performance and indicate several important pathways for further device refinement.

_{0.75}

Enabled by a heteroepitaxial nucleation process that yields GaP-on-Si integration free of heterovalent-related defects, GaP/active-Si junctions were grown by metalorganic chemical vapor deposition. n-type Si emitter layers were grown on p-type (1 0 0)-oriented Si substrates, followed by the growth of n-type GaP window layers, to form fully active subcell structures compatible with integration into monolithic III-V/Si multijunction solar cells. Fabricated test devices yield good preliminary performance characteristics and demonstrate great promise for the epitaxial subcell approach. Comparison of different emitter layer thicknesses, combined with descriptive device modeling, reveals insight into recombination dynamics at the GaP/Si interface and provides design guidance for future device optimization. Additional test structures consisting of GaP/active-Si subcell substrates with subsequently grown GaAsyP1-y step-graded buffers and GaAs0.75P0.25 terminal layers were produced to simulate the optical response of the GaP/Si junction within a theoretically ideal dual-junction solar cell.

P

Electron channeling contrast imaging (ECCI) is used to characterize misfit dislocations in heteroepitaxial layers of GaP grown on Si(100) substrates. Electron channeling patterns serve as a guide to tilt and rotate sample orientation so that imaging can occur under specific diffraction conditions. This leads to the selective contrast of misfit dislocations depending on imaging conditions, confirmed by dynamical simulations, similar to using standard invisibility criteria in transmission electron microscopy (TEM). The onset and evolution of misfit dislocations in GaP films with varying thicknesses (30 to 250 nm) are studied. This application simultaneously reveals interesting information about misfit dislocations in GaP/Si layers and demonstrates a specific measurement for which ECCI is preferable versus traditional plan-view TEM.

_{0.25}

The development and demonstration of methodologies for the heteroepitaxy of GaP on Si substrates, free of heterovalent interface related defects, and the subsequent metamorphic grading in the GaAsyP1-y alloy system necessary to achieve target III-V materials at sufficiently high quality, directly enable the achievement of monolithically-integrated multijunction solar cells utilizing both III-V and Si active sub-cells. Such devices hold promise for high photovoltaic performance at significantly reduced costs afforded by the Si platform. In this vein, early-stage prototype all-epitaxial GaAs0.75P0.25/Si dual-junction devices have been grown by a combination of MOCVD and MBE, demonstrating great promise for such an approach, and clear pathways for further improvement.

/Si Dual-Junction Solar Cells Grown by MBE and MOCVD

Post-growth surface morphologies of high-temperature homoepitaxial GaP films grown by molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) have been studied. Smooth, stepped surface morphologies of MBE-grown layers, measured by atomic force microscopy, were found for a wide range of substrate temperatures and P2:Ga flux ratios. A MOCVD-based growth study performed under similar conditions to MBE-grown samples shows a nearly identical smooth, step-flow surface morphology, presenting a convergence of growth conditions for the two different methods. The additional understanding of GaP epitaxy gained from this study will impact its use in applications that include GaP-based device technologies, III-V metamorphic buffers, and III-V materials integration with silicon.