John A. Nestor

Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench

1. Introduction.- 1.1. Synthesis of Integrated Circuits.- 1.2 The System Architects Workbench.- 1.3 Contrasting Approaches to Synthesis.- 1.4. Historical Note.- 1.5. Overview of the Book.- 2. Design Representations and Synthesis.- 2.1 The Model of Design Representation.- 2.2. Behavioral Representations at the ALGORITHMIC Level.- 2.3. Behavioral and Structural Representations at the REGISTER-TRANSFER Level.- 2.4. Modeling ALGORITHMIC and RT Level Synthesis.- 2.6 Summary.- 3. Transformations.- 3.1. Vtbody Transformations.- 3.2. SELECT Transformations.- 3.3. Adding Processes To The Workbench.- 3.4. Process Creation.- 3.5. Pipestage Creation.- 3.6. Structural Transformations.- 3.7. Summary.- 4. Architectural Partitioning (APARTY).- 4.1. Architectural Partitioning.- 4.2. Previous Work: Clustering.- 4.3. Multi-Stage Clustering.- 4.4. Methodology.- 4.5. Guiding Other Synthesis Tools.- 4.6. A Partitioning Example.- 4.7. Summary.- 5. Control Step Scheduling (CSTEP).- 5.1. The Scheduling Problem.- 5.2. Related Work.- 5.3. The CSTEP Scheduling Approach.- 5.4. Scheduling Examples.- 5.5. Summary.- 6. Data Path Allocation (EMUCS).- 6.1. Other Data Path Allocators.- 6.2. EMUCS Overview.- 6.3. Initialization.- 6.4. Prebinding and Manual Binding.- 6.5. Automatic Binding.- 6.6. Post-Processing.- 6.7. Finish Up.- 6.9. Summary.- 7. Microprocessor Synthesis (SUGAR).- 7.1. Organization of SUGAR.- 7.2. Behavioral Transformations.- 7.3. Execution Unit Organization Analysis.- 7.4. Code Generation.- 7.5. Code Selection.- 7.6. Register and Bus Assignment.- 7.7. Phase Structure of SUGAR.- 7.8. Summary.- 8. Synthesis Results.- 8.1. Fifth Order Digital Elliptic Wave Filter.- 8.2. Kalman Filter.- 8.3. BTL310.- 8.4. MCS6502.- 8.5. MC68000.- 8.6. Summary.- 9. Correlating the Multilevel Design Representation (CORAL).- 9.1 Linking Design Representations.- 9.2 Applications.- 9.3 Summary.- 10. Observations and Future Work.- 10.1. Are The Two Synthesis Paths Different?.- 10.2. You Need More Than Synthesis.- 10.3. Algorithmic Level Synthesis.- 10.4. Logic Synthesis, Module Generation and Physical Design.- 10.5. Design Languages.- 10.6. Summary.- References.

SALSA: a new approach to scheduling with timing constraints

A mechanical, play free drive for rotatable parts in particular in precision devices, which comprises a driven gear provided on the rotatable parts. A drive means drives the driven gear. A support element is in radial direction opposite to the driving means, and the driven gear is tong-like embraced by the drive means and the support element, for the most possible movement transmission free from forces.

Data path allocation using an extended binding model

Existing approaches to data path allocation in high-level synthesis use a binding model in which values are assigned to the same register for their entire lifetimes. The authors describe an extended binding model in which segments of a values lifetime may reside in different registers if there is a cost advantage in doing so. In addition, the model supports multiple copies of values and the use of functional units to pass through unmodified values to reduce interconnects. This model was exploited in an allocation tool that used iterative improvement to search for low-cost designs. Results showed that allocation costs can be substantially reduced by using this model.<<ETX>>

SALSA II: A fast transformational scheduler for high-level synthesis

An improved transformational approach to the scheduling problem in high-level synthesis is described. Based on an existing approach called SALSA, it uses an extended move set and lower bounds on resource costs to quickly find high-quality schedules of data-oriented control-data flow graphs. Results show the ability to find high-quality schedules for difficult scheduling problems in small amounts of CPU time. Results show that in contrast to other approaches, execution times can actually decrease as schedule length increases.<<ETX>>

Experience With the CADAPPLETS Project

The CADAPPLETS Project provides Web-based animations (implemented as applets) of very large scale integration (VLSI) computer-aided design (CAD) algorithms as a learning resource for electrical and computer engineering students, designers, and CAD tool developers. Concepts from software algorithm animation are adapted to illustrate the problem formulation and the operation of physical design algorithms for placement and routing. This paper surveys these animations and describes how they have been used in the classroom at Lafayette College, Easton, PA, by users over the Internet, and in courses at other universities worldwide.

L3: An FPGA-Based Multilayer Maze Routing Accelerator

This paper describes a multi-layer maze routing accelerator which uses a two-dimensional array of processing elements (PEs) implemented in an FPGA. Routing for an L-layer N X N grid is performed by an array of N X N PEs that time-multiplex each layer over the array. This accelerates the classic Lee Algorithm from O(L X d 2 ) in software to O(L X d). Each PE can be implemented in 32 look up tables

MIES: a microarchitecture design tool

This paper describes MIES, a design tool for the modeling, visualization, and analysis of VLSI microarchitectures. MIES combines a graphical data path model and symbolic control model and provides a number of user interfaces which allow these models to be created, simulated, and evaluated.

FPGA implementation of a maze routing accelerator

This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction.

Visual register-transfer description of VLSI microarchitectures

A new visual approach to creating and manipulating symbolic descriptions of VLSI microarchitectures at the register-transfer (RT) level is described. The MIES visual RT description provides a number of views of a microarchitectures datapath and controller that visually emphasize different aspects of a design. The key view ties together a symbolic description of the RT operations invoked by a controller with the flow and manipulation of data in the datapath. A prototype implementation demonstrates a number of interesting capabilities, which are illustrated using several examples. >

An undergraduate embedded systems project

Courses in embedded systems can approach the subject from a variety of perspectives, ranging from emphasis on hardware, emphasis on software, or emphasis on system design. This paper describes a course in embedded systems that requires students to develop software to control a system that is physically available in the laboratory. The hardware models a rapid transit system that is controlled using a distributed system consisting of five independent microcontrollers, communicating with each other via Ethernet. Designing the control software includes communicating with the other microcontrollers via UDP packets, communicating with the system hardware, and providing a web page to report status and accept system parameters such as tram speed and station waiting time. Students use an open-source operating system for their software, which they write in the C language; the operating system uses cooperative threads and provides library functions for serial and Ethernet input/output. The semester goal is to properly control as many trams as possible, with safety interlocks implemented. The physical system allows students to see the results of their software.