J. V. Rajan

Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench

1. Introduction.- 1.1. Synthesis of Integrated Circuits.- 1.2 The System Architects Workbench.- 1.3 Contrasting Approaches to Synthesis.- 1.4. Historical Note.- 1.5. Overview of the Book.- 2. Design Representations and Synthesis.- 2.1 The Model of Design Representation.- 2.2. Behavioral Representations at the ALGORITHMIC Level.- 2.3. Behavioral and Structural Representations at the REGISTER-TRANSFER Level.- 2.4. Modeling ALGORITHMIC and RT Level Synthesis.- 2.6 Summary.- 3. Transformations.- 3.1. Vtbody Transformations.- 3.2. SELECT Transformations.- 3.3. Adding Processes To The Workbench.- 3.4. Process Creation.- 3.5. Pipestage Creation.- 3.6. Structural Transformations.- 3.7. Summary.- 4. Architectural Partitioning (APARTY).- 4.1. Architectural Partitioning.- 4.2. Previous Work: Clustering.- 4.3. Multi-Stage Clustering.- 4.4. Methodology.- 4.5. Guiding Other Synthesis Tools.- 4.6. A Partitioning Example.- 4.7. Summary.- 5. Control Step Scheduling (CSTEP).- 5.1. The Scheduling Problem.- 5.2. Related Work.- 5.3. The CSTEP Scheduling Approach.- 5.4. Scheduling Examples.- 5.5. Summary.- 6. Data Path Allocation (EMUCS).- 6.1. Other Data Path Allocators.- 6.2. EMUCS Overview.- 6.3. Initialization.- 6.4. Prebinding and Manual Binding.- 6.5. Automatic Binding.- 6.6. Post-Processing.- 6.7. Finish Up.- 6.9. Summary.- 7. Microprocessor Synthesis (SUGAR).- 7.1. Organization of SUGAR.- 7.2. Behavioral Transformations.- 7.3. Execution Unit Organization Analysis.- 7.4. Code Generation.- 7.5. Code Selection.- 7.6. Register and Bus Assignment.- 7.7. Phase Structure of SUGAR.- 7.8. Summary.- 8. Synthesis Results.- 8.1. Fifth Order Digital Elliptic Wave Filter.- 8.2. Kalman Filter.- 8.3. BTL310.- 8.4. MCS6502.- 8.5. MC68000.- 8.6. Summary.- 9. Correlating the Multilevel Design Representation (CORAL).- 9.1 Linking Design Representations.- 9.2 Applications.- 9.3 Summary.- 10. Observations and Future Work.- 10.1. Are The Two Synthesis Paths Different?.- 10.2. You Need More Than Synthesis.- 10.3. Algorithmic Level Synthesis.- 10.4. Logic Synthesis, Module Generation and Physical Design.- 10.5. Design Languages.- 10.6. Summary.- References.

Synthesis by Delayed Binding of Decisions

This paper presents a method for the automatic synthesis of digital systems from behavioral descriptions. Subtasks in complex problem solving activities like synthesis often interact. As a result, premature binding of decisions can lead to poor designs. Better design choices can be made if decisions are postponed until adequate information is available to make them. The paper details how delayed binding of decisions is implemented in a program called SUGAR and how subtasks are organized so that they cooperate with one another in designing a system.

Linking the Behavioral and Structural Domains of Representation for Digital System Design

A means of linking together the behavioral and structural domains of representation is presented. The approach can be used in a design synthesis system where the input is an abstract behavior of the system to be designed. As transformations are made to the behavior and the logical structure is specified, this approach maintains the correspondences between the two. These correspondences are maintained even when numerous optimizing transformations are applied to the behavior and structure. The result is that the structure designed can be correlated with the initial behavioral description and feedback containing both can be produced for a system-level architect.

Observations and Future Work

While the research projects presented here combine to demonstrate Algorithmic and Register-Transfer Level Synthesis, they are far from the final solution. Rather they each have served to demonstrate basic concepts and approaches to the steps in synthesis, and together have shown two methods of integrating the steps into a synthesis system. In this Chapter, we make observations based on the results of the synthesis programs presented in the previous chapters and suggest future work in the area.

Control Step Scheduling (CSTEP)

Scheduling assigns operators in the behavioral specification to control steps that represent clock cycles in the completed design. Because scheduling and other design tasks are heavily interdependent, it has been recognized as an important part of the synthesis problem [Gajski86]. When interface information is added to the synthesis problem, scheduling becomes even more important because it determines whether timing constraints can be met in the resulting implementation.

DIF: a framework for VLSI multi-level representation

Abstract A new hierarchical interchange format is presented which provides the framework for communication between CAD tools within a VLSI design environment. DIF supports a true hierarchical multi-level design representation and maintains both structural and abstract representations of a design, as well as the inter-relationships between them. For a given design, a DIF description would consist of a set of hierarchically interconnected modules, to each of which is associated a set of attributes which are the abstract representations of these modules. These attributes can span the entire design hierarchy and take any form, such as behavioral specifications, datapath and control specifications, and circuit, logic, and layout representations. An implementation of DIF within the CMU design environment is discussed, and examples of the interaction between DIF and associated CAD tools are presented.

Microprocessor Synthesis (SUGAR)

The four previous chapters describe one approach to Algorithmic and Register-Transfer level synthesis. In contrast to these four separate design tools that work together, the SUGAR microprocessor synthesis tool combines elements of each of these tools. This chapter will highlight three issues in register-transfer synthesis by discussing how the organization of SUGAR differs from the previous approach. The issues are: how to handle interactions between the design steps and substeps in algorithmic and register-transfer level synthesis, the differences between style-specific and general-purpose synthesis methods, and the role of knowledge representation methods.

Correlating the Multilevel Design Representation (CORAL)

Previous chapters have discussed the actual process of synthesizing a structural design from a behavioral description. This chapter offers a method of preserving design information during that process. One of the problems encountered in many automated synthesis systems is that no information is provided describing the relationships between the various intermediate representations of the design that exist in the system. One feeds a design specification into the system and receives an implementation, but the system does not describe the relationship between the input and output design representations.

Data Path Allocation (EMUCS)

Data path allocation encompasses several steps of the design process: the allocation of hardware, the binding of data flow operators and values to that hardware, and the appropriate interconnection of the hardware to realize the data-flow. The hardware allocated is at the functional block level and includes modules such as registers, functional units, and multiplexors. In general, Value Trace operators are bound to functional units, VT values are bound to registers or wires, and multiplexors and busses are used to steer data flow among the other components. The goal of data path allocation is to build a functional block level design that is both small and easily realizable with respect to the target technology.

Design Representations and Synthesis

Before describing each of the Workbench design tools in detail, it is important to understand both the conceptual and detailed models of design representation used by the tools. This chapter presents the Workbench’s models of design representation, and with this background, defines the synthesis steps implemented by the Workbench tools.