John C. Johnson

Realizing the benefits of structural test for Intel microprocessors

This paper traces the evolution of the distributed test strategy at Intel, covering both the tester platform, which is now on the 2nd generation, as well as the parallel evolution of the test content, which is optimized for this platform. We describe the distribution of Pentium/spl reg/ 4 processor test content between structural and functional platforms, associated fallout, and key issues encountered with content migration. Finally, we discuss future test content and platform trends as shaped by increasing device complexity and defect types.

Cost containment for high-volume test of multi-gb/s ports

The agenda of high volume manufacturing (HVM) test is cost. Equipment costs, throughput, factory overhead, yield, and many other parameters make up overall test costs. But the start of any cost optimization must start with a very clear perspective of what HVM test must achieve, and what it cannot afford to be responsible for. HVM test is mostly a screen to ensure that outgoing products meet established goals for quality defect rate and reliability. It cannot afford to duplicate design validation processes that do not efficiently support this primary screening goal. Multi-GB/s devices drive this distinction to a critical level.

Options for high-volume test of multi-Gb/s ports

Devices with multi-GB/s ports from a variety of suppliers are shipping in high-volume today. Common port standards such as PCI Express are proliferating along with specialty ports. The number of lanes in multi-GB/s port can usually be scaled to increase bandwidth. The use of this serial/parallel port technology is growing as its bandwidth scaling, PCB trace out. Traditional SERDES devices with only 1 or 2 lanes had most yield fallout in the high-speed serial portion of the design. The industry responded with ATE instruments to expose those defects. Physical layer compliance testing is always a challenge and becomes overwhelming when coupled with multiple port types. In many cases, logic test patterns are applied through a multi-GB/s port at speed. The very high speed interfaces shows non-deterministic logic behavior.