Debendra Mallik

Thermal characteristics of single and multi-layer high performance PQFP packages

Using experimental and computational techniques, it is shown that significant reduction in the package thermal resistance can be achieved by using a multilayer lead frame structure for medium and high lead count plastic quad flat pack (PQFP) packages. The thermal resistance of the 132 lead PQFP is reduced by 38% and 43% with copper and alloy 42 lead frames, respectively, under natural convection. A three-dimensional finite-element thermal model is constructed and correlated with the experimental data. Using this model, it is demonstrated that the contribution of the low thermal conductivity insulating adhesive tape to the overall thermal resistance is about 1 ( degrees C/W). In addition, increasing the power and ground plane thicknesses from 6 to 10 mils results in only about 1.5 ( degrees C/W) improvement in the junction-to-ambient thermal resistance. The thermal model is used to compare the thermal characteristics of the single-layer and multilayer PQFPs with copper and alloy 42 lead frames in the multicomponent board environment. The comparison indicates that the thermal resistance of the multilayer/alloy 42 lead frame PQFPs approach the thermal resistance of the multilayer/copper lead frame packages as the board temperature rises above the ambient temperature as a result of board heating. These packages will have similar thermal performance if the board temperature rises about 70 ( degrees C) above the ambient. >

Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect

The EMIB dense MCP technology is a new packaging paradigm that provides localized high density interconnects between two or more die on an organic package substrate, opening up new opportunities for heterogeneous on-package integration. This paper provides an overview of EMIB architecture and package capabilities. First, EMIB is compared with other approaches for high density interconnects. Some of the inherent advantages of the technology, such as the ability to cost effectively implement high density interconnects without requiring TSVs, and the ability to support the integration of many large die in an area much greater than the typical reticle size limit are highlighted. Next, the overall EMIB architecture envelope is discussed along with its constituent building blocks, the package construction with the embedded bridge, die to package interconnect features. Next, the EMIB assembly process is described at a high level. Finally, high bandwidth signaling between the die is discussed and the link bandwidth envelope is quantified.

Packaging alternatives for high lead count, fine pitch, surface mount technology

It is noted that increasing demand for more powerful, small-form-factor personal computers is driving the need for highly integrated, high-performance, high-density, and low-cost component packaging, and that surface mount technology (SMT) has proved effective in meeting these needs. At the same time component technology is being relied upon to deliver high integration and high performance. While the future direction for packaged surface mount components seems clearly dominated by plastic encapsulation, there are a number of options using direct attachment of unpackaged die that achieve greater system density. The authors review both the alternatives and issues associated with the growing number of fine pitch surface mount and direct attach technologies that seem applicable for assembly of high-lead-count, high-integration IC devices. >

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS

A wireless sensor node (WSN) integrates a 0.79mm2 near-threshold voltage (NTV) 32-bit Intel Architecture (IA) microcontroller (MCU) in 14nm tri-gate CMOS, along with solar cell, energy harvester, flash memory, sensors and Bluetooth Low Energy (BLE) radio, to enable always-on always-sensing (AOAS) and advanced edge computing capabilities in Internet-of-Things (IoT) systems. The MCU features four independent voltage-frequency islands (VFI), a low-leakage SRAM array, an on-die oscillator clock source capable of operating at sub-threshold voltage, power gating and multiple active/sleep states, managed by an integrated power management unit (PMU). The MCU operates across a wide frequency (voltage) range of 297MHz (1V) to 0.5MHz (308mV), and achieves a peak energy efficiency of 17pJ/cycle at an optimum supply voltage (VOPT) of 370mV, operating at 3.5MHz. The WSN, powered by a solar cell, demonstrates sustained MHz AOAS operation, consuming only 360μW.

Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities

After decades of following the roadmap laid out by Moore’s law [1], silicon features have reached the nanoscale, which is below 100 nm in dimension, as illustrated in Fig. 22.1. The first logic products with 90-nm transistors, using the traditional silicon dioxide insulator and polysilicon gate, went into volume production in 2003. More recently in 2007, 45-nm devices using a revolutionary high-k metal gate transistor technology have been introduced [2, 3]. These nanoscale devices enable higher performance circuits, which in turn drive advanced features in their packaging. These devices can significantly lower the power consumption of high-performance logic products creating new applications in the fast-growing ultramobile market (Fig. 22.2) and thus requiring packaging to support the demands of these form factors. This chapter will discuss the challenges and opportunities in flip chip packaging for these nanoscale devices.

Advances and Challenges in Flip-Chip Packaging

The role of semiconductor packaging has evolved from space transformation and environmental protection, to becoming an important enabler for silicon and system performance. This paper examines some of the advances in flip-chip packaging as an enabler of power delivery and power removal using a microprocessor as an example. In addition, the role of the package as an enabler of system I/O performance and silicon back-end reliability will be examined

A new technique for measuring the inductance of pin grid array packages

A technique for measuring the inductance of pin-grid-array packages is described. It includes the design of a board that allows the measurements of inductance to values less than 10 pH. The board is unique in that it allows measurement of the inductance and resistance of 132-lead packages in less than an hour. The board was designed to allow testing of the package inductance with current sourced through multiple power pins and sunk through multiple ground pins. This measurement technique gives a true measure of the inductance with respect to the package ground loop, making possible the determination of the variation of the power and ground loop inductance from package to package. The authors discuss the design of the test board and how the board was modeled to remove the inductance, capacitance, and resistance of the board itself. The method is compared with the conventional technique for measuring inductance, and sample data for both methods are presented and compared. Results obtained by measuring the resonant frequency of the test boards show that the new method is more accurate than the old one.<<ETX>>