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Dive into the research topics where Sairam Agraharam is active.

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Featured researches published by Sairam Agraharam.


electronic components and technology conference | 2006

Copper die bumps (first level interconnect) and low-K dielectrics in 65nm high volume manufacturing

Andrew W. Yeoh; Margherita Chang; Christopher M. Pelto; Tzuen-Luh Huang; Sridhar Balakrishnan; Gerald S. Leatherman; Sairam Agraharam; Guotao Wang; Zhiyong Wang; Daniel Chiang; Patrick Stover; Peter Brandenburger

The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILDs) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains


electronic components and technology conference | 2004

Test vehicle to characterize silicon to organic flip chip package thermomechanical interactions

Dongming He; Sriram Srinivasan; Sairam Agraharam; Biju Chandran; Mike Mello; Pankaj Sinha; Vasu Atluri

The thermomechanical interaction of organic flip chip assembly is primarily driven by the coefficient of thermal expansion (CTE) mismatch between die and package. This, in addition to emerging constraints like mechanically weaker silicon inter-layer dielectrics, lead free assembly and tighter bump pitch, etc., significantly increase the assembly yield and reliability challenges. Electrically sensitive short loop assembly test vehicles with representative product design features provide quick data turn and more coverage than live products to address these interconnect concerns. Yield and reliability data plus stress modeling and experimental measurements from assembly test vehicles highlight the importance of silicon and package test structures to understand die to package CTE mismatch induced stress, helping to identify the weak links in packaging architecture from materials, process and design.


Archive | 2004

Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat

Gregory M. Chrysler; Abhay A. Watwe; Sairam Agraharam; Kramadhati V. Ravi; C. Garner


Archive | 2003

Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems

Sairam Agraharam; Carlton Hanna; Vasudeva Atluri; Dongming He


Archive | 2011

3D integrated circuit package with window interposer

Debendra Mallik; Ram S. Viswanath; Sriram Srinivasan; Mark Bohr; Andrew W. Yeoh; Sairam Agraharam


Archive | 2005

Integrated circuit packages with reduced stress on die and associated methods

Sairam Agraharam; Carlton Hanna; Vasudeva Atluri; Dongming He


Archive | 2015

INTERCONNECT STRUCTURES WITH POLYMER CORE

Sandeep Razdan; Edward R. Prack; Sairam Agraharam; Robert L. Sankman; Shan Zhong; Robert Nickerson


Archive | 2012

FLEXIBLE COMPUTING FABRIC

Aleksandar Aleksov; Ravindranath V. Mahajan; Sairam Agraharam; Ian A. Young; John C. Johnson; Debendra Mallik; John S. Guzek


Archive | 2009

C4 joint reliability

Sairam Agraharam; Carlton Hanna; Dongming He; Vasudeva Atluri; Debendra Mallik; Matthew George O. Escobido; Sujit Sharan


Archive | 2012

WEARABLE IMAGING SENSOR FOR COMMUNICATIONS

Ravi Pillarisetty; Sairam Agraharam; John S. Guzek; Christopher J. Jezewski

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