John G. Holm

The Paradigm compiler for distributed-memory multicomputers

To harness the computational power of massively parallel distributed-memory multicomputers, users must write efficient software. This process is laborious because of the absence of global address space. The programmer must manually distribute computations and data across processors and explicitly manage communication. The Paradigm (PARAllelizing compiler for DIstributed-memory, General-purpose Multicomputers) project at the University of Illinois addresses this problem by developing automatic methods for the efficient parallelization of sequential programs. A unified approach efficiently supports regular and irregular computations using data and functional parallelism. >

Application of simple genetic algorithms to sequential circuit test generation

In this work we investigate the effectiveness of genetic algorithms (GAs) in the test generation process. We use simple GAs to generate populations of candidate test vectors and to select the best vector to apply in each time frame. A sequential circuit fault simulator is used to evaluate the fitness of each candidate vector, allowing the test generator to be used for both combinational and sequential circuits. We experimented with various GA parameters, namely population size, number of generations, mutation rate, and selection and crossover schemes. For the ISCAS85 combinational benchmark circuits, 100% of testable faults were detected in six of the ten circuits used, and very compact test sets were generated. Good results were obtained for many of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.<<ETX>>

Compilation of scientific programs into multithreaded and message driven computation

Many programs written in the SPMD programming model send messages asynchronously, and block when receiving messages. Multiple threads can make use of the processor while other threads wait for messages. This paper describes and evaluates two techniques for multithreading on the nodes of distributed memory message passing systems. One method is a purely runtime threads package. The second method requires the SPMD code to be systematically transformed into message driven code which can be run under a message driven model. The multithreading of scientific applications is evaluated on the iPSC2 and the CM5.<<ETX>>

Performance evaluation of a C++ library based multithreaded system

One model of multithreading gaining popularity on multiprocessor systems is the message driven model of computation. The message driven model is a reactive model in which an arriving message starts a block of computation to process that message. The advantage of programming in such a model is that the dependencies are explicit, messages are asynchronous, and the resulting code is highly multithreaded. The message driven model studied in the paper is the actor model of concurrent computation. The paper presents an empirical performance study of the runtime and kernel support of the ProperCAD II C++ class library which supports the actor model. The ProperCAD II C++ class library facilitates the use of multithreading on parallel platforms through object oriented design techniques. The usefulness of the ProperCAD II is shown through the results of various large, real applications. In addition to providing a useful paradigm to program complex parallel applications, we believe that the actor model integrates well with more advanced performance feedback and visualization tools. Further feedback related to multithreading will be presented in the form of dynamically weighted actor method call graphs, method specific statistics, and program visualization.

Performance evaluation of message-driven parallel VLSI CAD applications on general purpose multiprocessors

This paper presents a detailed evaluation of parallel mesaagedriven pmgmms on both message-passing and shared memory pamllel architectures. Four large pomllel appiications from the domain of VLSI computer aided design are evaluated, namely: parallel test pattern genemtion, pamllel cell placement, logic qnthesis, and event dn’ven VHDL kmulalion. The parallelism structure, the communication characterktics, locality chamcterirrtics, gmin sizes of wmputationa, and detailed measurement8 of system time, idle time, and uaer time are meaaunzd for theae applicationa. Resulta are presented for an Intel Pamgon distributed-memory measagepassing multicomputer and compared to a Sun SPARCcenter 1 OOOE symmetric multiprocessor.