José E. Franca

Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.

New CMOS logarithmic A/D converters employing pipeline and algorithmic architectures

New techniques for realizing CMOS logarithmic analog-to-digital (A/D) converters employing pipeline and algorithmic architectures are described. This is achieved by replacing the operations of subtraction/addition and multiplications in their linear counterparts by simple scaling operations in the logarithmic domain. Logarithmic pipeline A/D converters are more appropriate for high-frequency applications whereas logarithmic algorithmic A/D converters are particularly suitable for compact, low-cost designs. Examples are given to illustrate the proposed techniques.

Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems

This paper analyzes the output phase-skew effects related to practical sample-and-hold embedding in high-speed, time-interleaved sampled-data systems. Closed-formed expressions are presented and verified by numerical computer simulations. Special design techniques and layout issues for reducing both the random process and systematic mismatches are presented through a real application of a low phase-skew clock generation circuit that is used for a very high-frequency SC multirate filter with 320 MHz output sampling rate. Measurement results (skew noise tones <-72 dBc) further verify the proposed techniques.

High-speed D/A conversion with linear phase sin x/x compensation

A design technique is described for the realization of a digital-to-analog (D/A) conversion system with an embedded finite impulse response (FIR) filtering function suitable for the compensation of the sin x/x distortion introduced by fully sampled-and-held signals and which is attractive for integrated circuit implementation from the viewpoints of area and power consumption. This is demonstrated for an 8-b D/A conversion prototype system with an associated 3-tap 5-b precision FIR filtering function that has been fabricated using a 1.2-/spl mu/m digital CMOS technology.<<ETX>>

A CMOS steering-current multiplying digital-to-analog converter

This paper discusses the design and integrated circuit implementation of two alternative solutions for realizing an 8-bit high-speed steering-current multiplying digital-to-analog converter based on a current-source-array architecture. In the first solution, designated as voltage-controlled-current-source operation, a reference voltage is used to drive directly the gate-to-source voltage of the current-sources while in the second solution, designated as geometry-programmable-current-source operation, the current-sources are generated using a digitally programmable transistor-array. The characteristics of both solutions are discussed from the viewpoints of the accuracy and distortion introduced by the multiplying function. For demonstration purposes a prototype chip suitable for both operating modes has been fabricated in a single-poly 1.2µm CMOS digital technology. At 5 V supply and 13.3 mA full-scale output current, the chip dissipates about 90 mW for a sampling frequency of 50 MHz. The die area is approximately 1.75 mm2.

A comparative study of two adaptive continuous-time filters for decision feedback equalization read channels

This paper presents a comparative study of two adaptive continuous-time 3rd order allpass equalizers for magnetic disk decision feedback equalization read channels. These are based on adaptive current-mode Gm-C structures employing low-mismatch high bandwidth pseudo-differential balanced transconductors and polarized MOSFET arrays as integrating capacitors. Transistor level simulation results are presented to demonstrate the performance characteristics of both structures.

High-speed CMOS current comparators

We present in this paper two high-speed current comparators which are fully compatible with digital CMOS technology, occupy little silicon area and dissipate low power. Experimental results are presented to demonstrate the performance of these circuits.<<ETX>>

An analogue self-calibration technique for high-resolution video-rate pipelined A/D converters

An analogue self-calibration technique employing a high-linearity pulse-counting reference DAC for code-by-code correction is proposed for calibrating both the MDAC nonlinearities and the interstage-gain errors in high-resolution video-rate pipelined analogue-to-digital converters. When compared with alternative code-by-code calibration techniques, the proposed solution has the advantage of correcting also the residue-amplification gain of the calibrated stages while using similar additional resources. An example is presented which reveals the effectiveness of such solution.

High-linearity calibration of low-resolution digital-to-analog converters

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages.<<ETX>>

A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structures low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.