Anant Singh

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

Low-voltage-swing logic circuits for a 7GHz x86 integer core

Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.

Low voltage swing logic circuits for a Pentium 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

To meet advancing market demands, microprocessor embedded memory applications require denser and faster memory arrays with each process generation. Recent work presented an 18.5ns 128Mb DRAM with a floating body cell for conventional DRAM products [1] and a 4Mb memory macro using a memory cell built with two floating body transistors [2]. This paper presents a floating-body Z-RAM® memory cell [3] to fabricate a high-density low-latency and high-bandwidth 4Mb memory macro building block, targeted at the requirements of microprocessor caches. It uses a single transistor (1T), unlike traditional 1T1C DRAM [4], or six transistor 6T-SRAM memory cells [5].

26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology

The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high-insertion-loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of electrical channels by lowering the signal spectrum. Such an approach suffers from lower SNR tolerance as well as higher susceptibility to crosstalk and ISI as compared to differential signaling (DS). Coded differential approaches have been reported [2] to mitigate ISI. Our approach is a generalization of DS in which ternary values are transmitted on an 8-wire bus. The set of transmitted values belongs to a code consisting of 256 code-words called the 8b8w-code (8-bits-on-8-wires) [3]. The specific correlations in the code-words of the 8b8w-code eliminate transmit common-mode and simultaneous switching output (SSO) noise and allow for detection via self-referencing comparators (unlike PAM-4), which provides additional noise immunity. Compared to DS, the 8b8w-code offers twice the throughput at 50% of the line power. Compared to PAM-4, the code offers better SNR (3dB) at 38% of the line power with enhanced tolerance of ISI and lower crosstalk generation. The design and experimental verification of an 8b8w transceiver in 40nm CMOS is described. Transmission is achieved up to 12Gb/s per wire over 55cm of Rogers with up to 15dB loss.

A mixed signal rotator/shifter for 8GHz Intel/spl reg/ Pentium/spl reg/ 4 integer core

A novel mixed signal 32-bit rotator/shifter circuit design enabling ultra-short latency Intel/spl reg/ Netburst/spl trade/ rotate and shift instructions is described. Compared to previous generation Intel/spl reg/ Pentium/spl reg/ 4 processor designs, this implementation cuts Rotate/Shift latency and throughput by 75% while adding significant frequency headroom. The circuit manufactured on Intels 90nm process confirms a significant boost in integer performance.