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Dive into the research topics where John L. Sturtevant is active.

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Featured researches published by John L. Sturtevant.


26th Annual International Symposium on Microlithography | 2001

Toward 0.1-μm contact hole process by using water-soluble organic overcoating material (WASOOM)-- Resist flow technology III: study on WASOOM, top flare, and etch characterization

Jun-Sung Chun; Chang Ho Maeng; Mark R Tesauro; John L. Sturtevant; Joseph E. Oberlander; Andrew R. Romano; John P. Sagan; Ralph R. Dammel

In our previous experiment for sub-0.15micrometers contact hole, we used water-soluble organic over-coating material (for short: WASOOM) as a barrier layer to distribute thermal stress evenly from top to bottom of contact hole resist. It is assumed that WASOOM inside a contact hole will be acting as a barrier layer (or buffer) so that overhang can be reduced. In this paper we will describe a 0.1micrometers contact hole process with well controlled DICD and good etch profile. In order to get a good WASOOM for this study, lots of water soluble polymers have been evaluated. Our methods for resist flow technique use WASOOMs property that it should not react with photoresist at high temperature. The criteria and chemistry of good WASOOM materials will be described for further study. In addition to WASOOM material, we will also explain the results of top flare by using PVP based WASOOM and appropriate etch processes. For etching characterization, we used C5F8 chemistry for the initial study and then later on it is found that there is some etch stop issue which appears related to surface carbon contamination of the etch front coming from C5F8. This surface contamination issue will be also investigated. Mixed C5F9/CF4 chemistry was introduced to make a more robust etching process. This uses the carbon polymerization of C5F8 for good etching profile and adds a small portion of CF4 to generate radical CF species which will prevent etch stop.


Metrology, Inspection, and Process Control for Microlithography XVII | 2003

Single wafer process to generate reliable swing

Yiming Gu; Cynthia Zhu; John L. Sturtevant

Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.


Metrology, Inspection, and Process Control for Microlithography XVII | 2003

Resist compacting under SEM E-Beam

Yiming Gu; Dyiann Chou; John L. Sturtevant

Resist critical dimensions (CD) and thickness are usually obtained by in-line CD SEM or in-line optical metrology measurements but varification or calibration of these is typically achived by cross sectional SEM. As we push CDs to 100nm and beyound, descrepencies between these two sources data can constitute a large percentage of the target dimension. Particularly for 193nm resists, the CD shrinkage under SEM has been well characterized, but the vertical and horizontal compaction behavior in across sectional SEM has not been explored. In this paper, the discussion is divided into two parts. One is for bulk resist and another is for patterned resist. For bulk case, the the only variable is vertical thickness. The experiments for I-line, 248nm and 193nm resist indicated that the resist thickness from the cross sectional image is strongly dependent on the resist polymer structure, the SEM conditions and the interrogration time under SEM E-beam. Therefore, the thickness comparison between optical and electronic is not always meaningful because the cross sectional thickness often shows a low thickness than the optically determined value. We have determined the optimum SEM condition to minimize vertical compaction. There are two variables for patterned resist, vertical thickness and lateral CD size. Our experiments for I-line and 248nm resists exhibited that the patterned resist thickness can be 30% lower than the optical thickness. However, the lateral CD sizes showed less variation relative to the different SEM conditions. The unique behaviors of 193nm patterned resist are also displayed and discussed in this paper. Based on all experimental data, different SEM conditions are recommended based on different purposes to generate accurate cross sectional resist images.


Advanced Process Control and Automation | 2003

Improving overly manufacturing metrics through application of feedforward mask-bias

Etienne Joubert; Joseph Pellegrini; Manish Misra; John L. Sturtevant; John M. Bernhard; Phu Ong; Nathan K. Crawshaw; Vern Puchalski

Traditional run-to-run controllers that rely on highly correlated historical events to forecast process corrections have been shown to provide substantial benefit over manual control in the case of a fab that is primarily manufacturing high volume, frequent running parts (i.e., DRAM, MPU, and similar operations). However, a limitation of the traditional controller emerges when it is applied to a fab whose work in process (WIP) is composed of primarily short-running, high part count products (typical of foundries and ASIC fabs). This limitation exists because there is a strong likelihood that each reticle has a unique set of process corrections different from other reticles at the same process layer. Further limitations exist when it is realized that each reticle is loaded and aligned differently on multiple exposure tools.A structural change in how the run-to-run controller manages the frequent reticle changes associated with the high part count environment has allowed for breakthrough performance to be achieved. This breakthrough was mad possible by the realization that; 1. Reticle sourced errors were highly stable over long periods of time, thus allowing them to be deconvolved from the day to day tool and process drifts. 2. Reticle sourced errors can be modeled as a feedforward disturbance rather than as discriminates in defining and dividing process streams. In this paper, we show how to deconvolve the static (reticle) and dynamic (day to day tool and process) components from the overall error vector to better forecast feedback for existing products as well as how to compute or learn these values for new product introductions - or new tool startups. Manufacturing data will presented to support this discussion with some real world success stories.


SPIE's 27th Annual International Symposium on Microlithography | 2002

Reduction of reflective notching through illumination optimization

James C. Word; Dyiann Chou; Yiming Gu; John L. Sturtevant

Photolithography on reflective surfaces with topography can cause exposure in unwanted areas, resulting in the phenomenon of reflective notching. Solutions to this problem are known within the industry, including the use of bottom anti-reflective coatings (ARCs) and dyed photoresist. In certain situations, such as on implant layers, the use of a BARC may be impractical. One potential solution to this problem lies in optimization of the illumination settings. It is known that changes in the illumination settings NA and sigma have an impact on the swing curve amplitude. It will be shown that for certain situations, reflective notching can be virtually eliminated through proper selection of the illumination settings.


Archive | 2004

Dynamically coupled metrology and lithography

John L. Sturtevant; Yiming Gu


Archive | 2002

Dual-layer deep ultraviolet photoresist process and structure

Yiming Gu; John L. Sturtevant; Anging Zhang


SPIE's 27th Annual International Symposium on Microlithography | 2002

Assist feature OPC implementation for the 130 nm technology node with KrF and no forbidden pitches

James C. Word; Siuhua Zhu; John L. Sturtevant


Archive | 2002

Method for generating a swing curve and photoresist feature formed using swing curve

Yiming Gu; John L. Sturtevant


Archive | 2002

Dual-wavelength exposure for reduction of implant shadowing

John L. Sturtevant; Yiming Gu; Dyiann Chou; Chantha Lom

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Yiming Gu

Integrated Device Technology

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Dyiann Chou

Integrated Device Technology

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James C. Word

Integrated Device Technology

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Anging Zhang

Integrated Device Technology

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Anqing Zhang

Integrated Device Technology

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Chang Ho Maeng

Integrated Device Technology

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Chantha Lom

Integrated Device Technology

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Cynthia Zhu

Integrated Device Technology

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John M. Bernhard

Integrated Device Technology

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Juliann Opitz

Integrated Device Technology

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