Yiming Gu

Performance Comparison between Attenuated PSM and Opaque MoSi on Glass (OMOG) Mask in Sub-32nm Litho Process

During the development of optical lithography that has been extending to 32 nm and beyond, it is found that the selection of mask blank types has a very strong impact on minimum feature process window, or critical dimension performance that can be achieved, which will affect ultimate wafer lithographic performance. Although the industry-standard 6% attenuated phase shifting mask (PSM) with 67nm MoSi has been widely used, as the manufacturing design rule continues to shrink, it will introduce quite a few challenges, such as, defect inspections, imaging contrast, or NILS, and mask error enhancement factor (MEEF) [1]. Meanwhile, the standard chrome-on-glass mask, compared with 6% Att. PSM, is unable to support the minimum feature required in lithographic process windows and through pitch requirements. To alleviate this problem, a new type of binary mask with Opaque MoSi On glass (OMOG) is gradually accepted and used in 32 nm. In this paper, both 6% attenuated PSM and OMOG mask have been evaluated with 28 nm patterns. PSM and OMOG masks critical dimension uniformities (CDU) are compared. Further more; we have also compared wafer line width roughness (LWR), After Development Inspection (ADI) CDU, MEEF, through pitch process window including Depth of Focus (DOF) and Exposure Latitude(EL). Our result shows that, for bright field and dark field mask, OMOG mask show different behavior than PSM mask in lithographic process performance. As above, whether OMOG can replace 6% attenuated PSM as 32 nm/28 nm main stream mask blank will depend on mask performance, litho performance, and device requirements.

Studying Photoresist Type for Sub-32nm Node Dense SRAM 2nd GT Layer

With continuous shrinking of device dimensions, high performance, dense SRAM cells design has become more challenging than before, patterning quality is also more sensitive to fluctuations in lithography process. This inevitably calls for more aggressive lithography process conditions in terms of the required resolution. The tradeoff between process window optimization for random logic gates and dense SRAM is not always straightforward, and it sometimes necessitates design rule and layout modifications. In particular, patterning the small tip-to-tip gap for dense SRAM cells at gate level becomes extremely challenging. By delinking patterning of SRAM tip-to-tip from other geometries, one can optimize the patterning processes independently at the expense of cost. This can be achieved through a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper, we will show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 32nm node. Besides illumination optimization, the selection of an appropriate photoresist and the development of good resist process conditions are found to play a key role to further improve the photolithographic process. The performance data, including process window, pattern profile accuracy, etc., from two different type photoresist samples are studied for SRAM 2 nd GT layer lithography process. For comparison purpose, we also present a single exposure single etch result for such dense SRAM cells. In the 45nm node, the dense SRAM cell can also be printed to adequate tolerances and process window under single exposure (SE) with OPC. We present our data on DE2, which indicate that it can be used as an alternative solution to pattern dense SRAM with good process extendibility.