John Liobe

Experimental Analysis of Substrate Noise Effect on PLL Performance

This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise transfer functions. It also leads to the conclusion that the PLL blocks other than the VCO can be more sensitive to substrate noise coupling, depending on the substrate noise frequency. Furthermore, the result shows that intermodulation near the reference clock frequency could be a dominant source of generating sidebands in fractional-N PLLs.

pbCAM: Probabilistically-banked Content Addressable Memory

Content Addressable Memories find wide use in network routers and certain image processing applications. However, their use is limited due to their high power demand resulting from their high activity factor. A banked CAM, on the other hand, partitions the entire CAM into smaller banks to cut down on excessive searches, while it may reduce the effective CAM size when the data entries are unevenly distributed. A new banked CAM design is introduced in this paper which achieves significant energy and power savings through the use of Bloom Filters by effectively decoupling data elements from their bank index. Simulation results show energy savings of nearly an order of magnitude.

Fault diagnosis of a GHz CMOS LNA using high-speed ADC-based BIST

This paper presents a fault isolation method using the digital signatures from a LNA BIST solution. The fault localization capabilities of the functional test and data analysis methods are demonstrated by circuit level simulation. Also a discussion of the efficacy of this method is given. Results showed that only 16% of the resistive faults examined here cannot be mapped to its specification location in the LNA.

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits

This paper proposes a new IDD sensor for built-in self-test (BIST) applications for digital, analog, and mixed-signal circuits. This novel, wide-band, nonintrusive, process and temperature-stable IDD sensor operates up to 230 MHz, which is 2.3X faster than previously proposed designs, and occupies 78.3% less area than another competing design. A BIST utilizing this novel IDD sensor is created and tested on numerous digital circuits, as well as on an op-amp and a mixer, achieving up to 90% fault coverage, while maintaining the performance of the circuit-under-test. The experiments were implemented in 0.18-m TSMC CMOS mixed-signal technology.

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80 degC. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMCs 0.18-mum RF CMOS process (TSMC18RF).

Non-intrusive testing methodology for CMOS RF LNAs

This paper proposes a non-intrusive testing methodology for CMOS RF LNAs using the gain of the LNA as a test response to examine the effects of a particular set of spot defects. The impact of four types of resistive bridging faults is analyzed on a practical LNA example. A performance threshold for each fault location is established. Initial results show not only that the use of an ADC is possible, but also that it is a highly accurate device for testing CMOS LNAs. A discussion about both the strengths and limitations of this approach is also included.

Indirect-Feedback Sigma-Delta Image Sensors: Theory, Modeling and Design

A novel architecture for a CMOS image sensor that incorporates a column-level sigma-delta (ΣΔ) analog-to-digital converter is presented. An indirect-feedback readout architecture where the digital output of the ΣΔ modulator is accumulated by a digital counter and converted to an analog voltage that serves as the reference voltage in the modulators comparator is employed. A time-domain pixel simulator that enables assessment of the major noise contributions in this type of imager is also presented. Theoretical calculations agree with simulation results, showing a minimum readout noise of 2.18e- and a dynamic range (DR) of over 100 dB. Prototype chip tests without multiple resets show an 87 dB dynamic range with a readout noise of 2.17e-.

Experimental analysis of the effect of substrate noise on PLL performance

A novel approach is used to identify the substrate-noise sensitive components of a phase-locked loop (PLL) using a tank (LC) voltage controlled oscillator (VCO). Using passive noise injection pads capacitively connected to the substrate, continuous wave (CW) noise is injected into the substrate. The frequency response of the PLL is measured as noise is injected near dc, near the reference clock frequency, and near the VCO frequency. Analyzing the spurs seen in a spectrum analyzer leads to the conclusion that the other PLL blocks can be more sensitive to substrate noise coupling than the VCO, depending on the substrate noise frequency

Process tolerant calibration circuit for PLL applications with BIST

A process-invariant calibration circuit, capable of correcting performance errors in charge-pump based PLLs is described. Process variations detrimentally affect all building blocks of standard PLL architectures. Utilizing a novel ADC, these variations are sensed and corrected. The self-calibration circuitry is non-intrusive and requires minimal area and power overhead. A case study of a 2.4GHz ring VCO-based PLL designed in a TSMCs 0.18mum CMOS mixed-signal technology is given. The calibration circuitry is able to sense and calibrate under all four process corners as well as detect under high temperature conditions

A circuit-sensitive methodology for evaluating substrate noise

The paper proposes a practical methodology for analyzing the impact of substrate noise in any sensitive circuit. From this methodology, a figure of merit (FOM) is presented which can be used to compute the sensitivity of a circuit node to substrate noise. Simulations of a CMOS LNA prove the usefulness of this approach as an expeditious, yet effective, means for determining the portions of a circuit most sensitive to substrate noise.