John M. Carulli

Impact of negative bias temperature instability on product parametric drift

A systematic test methodology is presented that comprehends the impact of negative bias temperature instability on product parametric drift. In specific NBTI degradation mechanisms in digital CMOS circuits and transistors are presented. A test guard-banding technique to estimate parameter drift under BI and customer use conditions is also given.

Product drift from NBTI: Guardbanding, circuit and statistical effects

Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time, we report a monotonic reduction in variance of the log parameters (Ln(ΔF/F) and Ln(ΔID/ID)) as a function of stress time. A stochastic guard banding model accounting for time-dependent variance, re-ordering effects and granularity of data is demonstrated.

Parametric counterfeit IC detection via Support Vector Machines

We present a method to detect a common type of counterfeit Integrated Circuits (ICs), namely used ones, from their brand new counterparts using Support Vector Machines (SVMs). In particular, we demonstrate that we can train a one-class SVM classifier using only a distribution of process variation-affected brand new devices, but without prior information regarding the impact of transistor aging on the IC behavior, to accurately distinguish between these two classes based on simple parametric measurements. We demonstrate effectiveness of the proposed method using a set of actual fabricated devices which have been subjected to burn-in test, in order to mimic the impact of aging degradation over time, and we discuss the limitations and the potential extensions of this approach.

A TDC-based test platform for dynamic circuit aging characterization

An on-chip 45nm test platform that directly monitors circuit performance degradation during dynamic operation is demonstrated. In contrast to traditional ring-oscillator (RO) based frequency measurements, it utilizes a Time-to-Digital Converter (TDC) with 2ps resolution to efficiently monitor circuit delay change on-the-fly. This new technique allows the capability of measuring signal edge degradation under various realistic circuit operating scenarios, such as asymmetric aging, dynamic voltage/frequency scaling, dynamic duty cycle factors, and temperature variations.

Quality improvement and cost reduction using statistical outlier methods

Quality improvement and cost reduction in the overall IC manufacturing and test processes are being continuously sought. Outlier screening methods can address both of these needs. As technology scales, it has become increasingly difficult to screen outliers without excessive Type I or II errors. Hundreds of parameters are collected at wafer probe, but there lacks a systematic way of selecting outlier screens. In this paper we describe a statistical approach to both identify outliers and select beneficial screening parameters more effectively. Results on a 90nm design to reduce the burn-in fails are described.

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry

As the supply chain of electronic circuits grows more complex, with parts coming from different suppliers scattered across the globe, counterfeit integrated circuits (ICs) are becoming a serious challenge which calls for immediate solutions. Counterfeiting includes re-labeling legitimate chips or illegitimately replicating chips and deceptively selling them as made by the legitimate manufacturer, or simply selling fake chips. Counterfeiting also includes providing defective parts or simply previously used parts recycled from scrapped assemblies. Obviously, there is a multitude of legal and financial implications involved in such activities and even if these devices initially work, they may have reduced lifetime and may pose reliability risks. In this tutorial, we provide a comprehensive review of existing techniques which seek to prevent and/or detect counterfeit integrated circuits. Various approaches are discussed and an advanced machine learning-based method employing parametric measurements is described in detail.

Test data analytics — Exploring spatial and test-item correlations in production test data

The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item correlations in the test data for test time and cost reduction. We first describe a statistical regression method, called group lasso, which can identify inter-test-item correlations from test data. After learning such correlations, some test items can be identified for removal from the test program without compromising test quality. An extended version of this method, weighted group lasso, allows taking into account the distinct test time/cost of each individual test item in the formulation as a weighted optimization problem. As a result, its solution would favor more costly test items for removal from the test program. We further integrate weighted group lasso with another statistical regression technique, virtual probe, which can learn spatial correlations of test data across a wafer. The integrated method could then utilize both spatial and inter-test-item correlations to maximize the number of test items whose values can be predicted without measurement. Experimental results of a high-volume industrial device show that utilizing both spatial and inter-test-item correlations can help reduce test time by up to 55%.

Spatial correlation modeling for probe test cost reduction in RF devices

Test cost reduction for RF devices has been an ongoing topic of interest to the semiconductor manufacturing industry. Automated test equipment designed to collect parametric measurements, particularly at high frequencies, can be very costly. Together with lengthy set up and test times for certain measurements, these cause amortized test cost to comprise a high percentage of the total cost of manufacturing semiconductor devices. In this work, we investigate a spatial correlation modeling approach using Gaussian process models to enable extrapolation of performances via sparse sampling of probe test data. The proposed method performs an order of magnitude better than existing spatial sampling methods, while requiring an order of magnitude less time to construct the prediction models. The proposed methodology is validated on manufacturing data using 57 probe test measurements across more than 3,000 wafers. By explicitly applying probe tests to only 1% of the die on each wafer, we are able to predict probe test outcomes for the remaining die within 2% of their true values.

Successful Development and Implementation of Statistical Outlier Techniques on 90nm and 65nm Process Driver Devices

Burn-in and the concomitant post-burn-in retest are significant cost adders to the overall IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit analyses with parametric or non-parametric statistics, when applied to the newest technologies, result in excessive Type I or II errors which cannot be tolerated. In this paper, we describe the results from applying statistical burn-in avoidance techniques using time-zero sort test responses to driver designs fabricated in 90nm and 65nm low leakage technologies and libraries

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests

In an effort to reduce the cost of specification testing in analog/RF circuits, spatial correlation modeling of wafer-level measurements has recently attracted increased attention. Existing approaches for capturing and leveraging such correlation, however, rely on the assumption that spatial variation is smooth and continuous. This, in turn, limits the effectiveness of these methods on actual production data, which often exhibits localized spatial discontinuous effects. In this work, we propose a novel approach which enables spatial correlation modeling of wafer-level analog/RF tests to handle such effects and, thereby, to drastically reduce prediction error for measurements exhibiting discontinuous spatial patterns. The core of the proposed approach is a k-means algorithm which partitions a wafer into k clusters, as caused by discontinuous effects. Individual correlation models are then constructed within each cluster, revoking the assumption that spatial patterns should be smooth and continuous across the entire wafer. Effectiveness of the proposed approach is evaluated on industrial probe test data from more than 3,400 wafers, revealing significant error reduction over existing approaches.